LTC2259-16 LINER [Linear Technology], LTC2259-16 Datasheet - Page 17

• Manufacturer Part Number: LTC2259-16
• Description: 16-Bit, 80Msps Ultralow Power 1.8V ADC
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
For applications where the sample rate needs to be changed
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
make the sampling clock have a 50%(±5%) duty cycle. The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
The LTC2259-16 can operate in three digital output
modes: full-rate CMOS, double-data rate CMOS (to halve
the number of output lines), or double-data rate LVDS
(to reduce digital noise in the system). The output mode
is set by mode control register A3 (serial programming
mode), or by SCK (parallel programming mode). Note that
double-data rate CMOS cannot be selected in the parallel
programming mode.
Full-Rate CMOS Mode
In full-rate CMOS mode the 16 digital outputs (D0-D15),
and the data output clocks (CLKOUT
CMOS output levels. The outputs are powered by OV
and OGND which are isolated from the A/D core power
and ground. OV
1.2V through 1.8V CMOS logic outputs.
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double-Data Rate CMOS Mode
In double-data rate CMOS mode, two data bits are mul-
tiplexed and output on each data pin. This reduces the
number of data lines by eight, simplifying board routing
and reducing the number of input pins needed to receive
the data. The 8 digital outputs (D0_1, D2_3, D4_5, D6_7,
D8_9, D10_11, D12_13, D14_15), and the data output
clocks (CLKOUT
The outputs are powered by OV
isolated from the A/D core power and ground. OV
range from 1.1V to 1.9V, allowing 1.2V through 1.8V CMOS
logic outputs.
DD
+
, CLKOUT
can range from 1.1V to 1.9V, allowing
–
) have CMOS output levels.
DD
and OGND which are
+
, CLKOUT
–
DD
) have
can
DD
For good performance the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF a digital buffer should be used.
Double-Data Rate LVDS Mode
In double-data rate LVDS mode, two data bits are multi-
plexed and output on each differential output pair. There
are 8 LVDS output pairs (D0_1
D14_15
(CLKOUT
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OV
isolated from the A/D core power and ground. In LVDS
mode, OV
Programmable LVDS Output Current
In LVDS mode, the default output driver current is 3.5mA.
This current can be adjusted by serially programming mode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A3. The internal termination helps absorb any refl ections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is increased by 1.6x to maintain about the same output
voltage swing.
–
) for the digital output data. The data output clock
+
DD
/CLKOUT
must be 1.8V.
–
) has an LVDS output pair.
+
/D0_1
DD
LTC2259-16
and OGND which are
–
through D14_15
17
225916f
+
/