AD7870 Analog Devices, AD7870 Datasheet - Page 4

• Manufacturer Part Number: AD7870
• Description: LC2MOS Complete/ 12-Bit/ 100 kHz/ Sampling ADCs
• Manufacturer: Analog Devices

TIMING CHARACTERISTICS
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
5
6
Specifications subject to chance without notice.
ABSOLUTE MAXIMUM RATINGS*
V
V
AGND to DGND . . . . . . . . . . . . . . . . . –0.3 V to V
V
REF OUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V to V
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to V
Digital Outputs to DGND . . . . . . . . . . . –0.3 V to V
Operating Temperature Range
Storage Temperature Range . . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300 C
Power Dissipation (Any Package) to +75 C . . . . . . . . . 450 mW
Derates above +75 C by . . . . . . . . . . . . . . . . . . . . . 10 mW/ C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
AD7870/AD7875/AD7876
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7870/AD7875/AD7876 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
Timing specifications in bold print are 100% production tested. All other times are sample tested at +25 C to ensure compliance. All input signals are
Serial timing is measured with a 4.7 k
t
t
SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
SDATA will drive higher capacitive loads but this will add to t
permanent damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above those listed in
the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
device reliability.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
6
7
3
4
DD
SS
IN
5
6
Commercial (J, K, L Versions – AD7870) . . . 0 C to +70 C
Commercial (K, L Versions – AD7875) . . . . . 0 C to +70 C
Industrial (A, B, C Versions – AD7870) . . . .–25 C to +85 C
Industrial (B, C Versions – AD7875/AD7876)
Extended (S, T Versions) . . . . . . . . . . . . . . –55 C to +125 C
is measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
is defined as the time required for the data lines to change 0.5 V when loaded with the circuits of Figure 2.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 C to +85 C
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –15 V to +15 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Limit at T
(J, K, L, A, B, C Versions)
50
0
60
0
70
57
5
50
0
0
100
370
135
20
100
10
100
60
120
200
0
0
0
MIN
, T
MAX
pull-up resistor on SDATA and SSTRB and a 2 k pull-up on SCLK. The capacitance on all three outputs is 35 pF.
1, 2
(V
DD
Limit at T
(S, T Versions)
50
0
75
0
70
70
5
50
0
0
100
370
150
20
100
10
100
60
120
200
0
0
0
12
= +5 V
since it increases the external RC time constant (4.7 k
DD
DD
DD
+0.3 V
+0.3 V
+0.3 V
MIN
5%, V
DD
, T
MAX
–4–
SS
= –5 V
Units
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
Figure 2. Load Circuits for Output Float Delay
a. High-Z to V
5%, AGND = DGND = 0 V. See Figures 9, 10, 11 and 12.)
a. V
Figure 1. Load Circuits for Access Time
OH
to High-Z
Conditions/Comments
CONVST Pulse Width
CS to RD Setup Time (Mode 1)
RD Pulse Width
CS to RD Hold Time (Mode 1)
RD to INT Delay
Data Access Time after RD
Bus Relinquish Time after RD
HBEN to RD Setup Time
HBEN to RD Hold Time
SSTRB to SCLK Falling Edge Setup Time
SCLK Cycle Time
SCLK to Valid Data Delay. C
SCLK Rising Edge to SSTRB
Bus Relinquish Time after SCLK
CS to RD Setup Time (Mode 2)
CS to BUSY Propagation Delay
Data Setup Time Prior to BUSY
CS to RD Hold Time (Mode 2)
HBEN to CS Setup Time
HBEN to CS Hold Time
OH
C
L
) and hence the time to reach 2.4 V.
WARNING!
b. High-Z to V
b. V
OL
to High-Z
L
ESD SENSITIVE DEVICE
= 35 pF
OL
REV. B