DS21610-DS21610SN Dallas Semiconducotr, DS21610-DS21610SN Datasheet
DS21610-DS21610SN
Related parts for DS21610-DS21610SN
DS21610-DS21610SN Summary of contents
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... GENERAL DESCRIPTION The DS21610 is a multirate, low-jitter clock adapter that converts E-carrier and T-carrier clocks to multiple PDH carrier clock rates. Two clock outputs are available that are frequency-locked to the input clock. The clock outputs along with an 8kHz frame- sync output can be phase-aligned to a frame-sync input ...
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PIN DESCRIPTION ......................................................................................................................3 1.1 C LXP610.........................................................................................................................3 OMPATIBILITY WITH 2. FUNCTIONAL DESCRIPTION......................................................................................................5 3. OUTPUT JITTER ..........................................................................................................................6 3 ..........................................................................................................................................6 ITTER RANSFER 4. OPERATING PARAMETERS .......................................................................................................8 5. PACKAGE INFORMATION ........................................................................................................13 6. REVISION HISTORY ..................................................................................................................15 Figure 1-1. Block Diagram ....................................................................................................................4 Figure ...
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... SEL 22 13 FSP 24 14 SYNCIN 1.1 Compatibility with LXP610 The DS21610 is pin compatible with the LXP610. Table 1-B. Pin Name Cross-Reference to LXP610 DS21610 LXP610 P3 P3 SYNCOUT FSO CLKOUT2 HFO CLKIN CLKI CLKOUT1 CLKO GND N.C. ...
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... Figure 1-1. Block Diagram ANALOG CLKIN PLL Dallas Semiconductor DS21610 SEL SYNCIN P1 FREQUENCY P2 PLL SELECT P3 LOGIC P4 FEEDBACK OUTPUT CIRCUIT DIVIDER FRAME SYNC GENERATOR CLKOUT2 CLKOUT1 SYNCOUT FSP ...
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... SYNCOUT is selectable. It can be one or one-half the clock period of CLKIN, centered on the rising edge of CLKIN. Pins are used to select the various clock rates and operational modes. list the various operational modes of the DS21610. CLKIN, CLKOUT1, and CLCKOUT2 are always frequency-locked. They can all be phase-locked to a system frame-sync pulse ...
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... NOTE: THE TYPICAL PEAK JITTER GAIN OF THE DS21610 IS ABOUT 1.6 FOR CONVERSION FROM T1 TO E1. THE TYPICAL PEAK-JITTER GAIN OF THE LEVEL ONE DEVICE IS ABOUT 1.1. HOWEVER, THE JITTER GAIN FOR THE DS21610 PEAKS IN THE 4kHz TO 8kHz RANGE, WHEREAS THE PEAK JITTER GAIN FOR THE LXP610 SPANS A GREATER FREQUENCY RANGE (20kHz TO 40kHz) ...
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... NOTE: THE TYPICAL PEAK JITTER GAIN OF THE DS2161 IS ABOUT 1.4 FOR CONVERSION FROM T1 TO E1. THE TYPICAL PEAK-JITTER GAIN OF THE LEVEL ONE DEVICE IS ABOUT 1.1. HOWEVER, THE JITTER GAIN FOR THE DS21610 PEAKS IN THE 4kHz TO 8kHz RANGE, WHEREAS THE PEAK JITTER GAIN FOR THE LXP610 SPANS A GREATER FREQUENCY RANGE (20kHz TO 40kHz). ...
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... OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS21610SN Storage Temperature Range Soldering Temperature Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied ...
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AC TIMING (Figure 4-1, Figure 4-2, Figure 4-3, PARAMETER Capture Range on CLKIN Lock Range on CLKIN CLKIN Duty Cycle SYNCIN Setup to CLKIN Rising SYNCIN Hold After CLKIN Rising SYNCIN Pulse Width CLKOUT1 Delay from CLKIN Rising CLKOUT1 Duty ...
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Figure 4-1. SYNCIN/CLKIN to CLKOUT1/SYNCOUT and CLKOUT2 CLKIN SINCIN CLKOUT1 CLKOUT1 SYNCOUT CLKOUT2 CLKOUT1 ...
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Figure 4-2. Output Frame-Sync Alignment When CLKOIT2 = 2 x CLKOUT1 CLKOUT1 (4.096MHz) CLKOUT2 (8.192MHz) SYNCOUT CLKOUT1 (3.088MHz) CLKOUT2 (6.176MHz) SYNCOUT Figure 4-3. Output Frame-Sync Alignment When CLKOUT2 = 3 x CLKOUT1 CLKOUT1 (2.56MHz or 2.048MHz) CLKOUT2 (7.680MHz or 6.144MHz) ...
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Figure 4-4. Output Frame-Sync Alignment When CLKOIT2 = 4 x CLKOUT1 CLKOUT1 (1.544MHz or 2.048MHz) CLKOUT2 (6.176MHz or 8.192MHz) SYNCOUT (short) SYNCOUT (long) Figure 4-5. Output Frame-Sync Alignment When CLKOUT2 = 5 x CLKOUT1 CLKOUT1 (1.544MHz) CLKOUT2 (7.720MHz) SYNCOUT 12 ...
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PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information www.maxim-ic.com/DallasPackInfo.) 16-Pin SO, 0.300" Body ...
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PLCC LTR MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.02 — B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 D 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 0.390 ...
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REVISION HISTORY REVISION 090100 Preliminary release 112700 Remove references to 3V operation 120600 Add FSP pin to block diagram 021501 Add mechanical drawings for PLCC package 060601 Added jitter specifications and pinout for all packages 082001 Added timing diagrams ...