DS1005

Manufacturer Part NumberDS1005
Description5-Tap Silicon Delay Line
ManufacturerDallas Semiconducotr
DS1005 datasheet
 


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FEATURES
All-silicon time delay
5 taps equally spaced
Delay tolerance ±2 ns or ±3%, whichever is
greater
Stable and precise over temperature and
voltage range
Leading and trailing edge accuracy
Economical
Auto-insertable, low profile
Standard 14-pin DIP, 8-pin DIP, or 16-pin
SOIC
Tape and reel available for surface-mount
Low-power CMOS
TTL/CMOS compatible
Vapor phase, IR and wave solderability
Custom delays available
Quick turn prototypes
Extended temperature range available
DESCRIPTION
The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 12 ns
to 250 ns, with an accuracy of 2 ns or 3%, whichever is greater. This device is offered in a standard 14-
pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin
SOICs are also available. Both enhanced performance and superior reliability over hybrid technology is
achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC
packaging. In order to maintain complete pin compatibility, DIP packages are available with hybrid lead
configurations. The DS1005 reproduces the input logic level at each tap after the fixed delay specified by
the dash number in Table 1. The device is designed with both leading and trailing edge accuracy. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call (972) 371–4348.
5-Tap Silicon Delay Line
PIN ASSIGNMENT
IN
1
14
V
CC
NC
2
13
NC
NC
3
12
TAP 1
TAP 2
4
11
TAP 2
NC
NC
TAP 3
5
10
TAP 4
6
9
NC
TAP 4
7
8
GND
TAP 5
DS1005 14-Pin DIP (300-mil)
GND
See Mech. Drawings Section
See Mech. Drawings Section
1
IN
2
TAP 2
TAP 4
3
GND
4
DS1005M 8-Pin DIP (300-mil)
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1-TAP 5 - TAP Output Number
V
- +5 Volts
CC
GND
- Ground
NC
- No Connection
IN
- Input
1 of 6
DS1005
IN
1
16
V
CC
NC
2
15
NC
NC
3
14
NC
4
13
TAP 1
NC
5
12
NC
TAP 3
6
11
NC
7
10
NC
9
8
TAP 5
DS1005S 16-Pin SOIC
(300-mil)
V
8
CC
7
TAP 1
6
TAP 3
5
TAP 5
111799

DS1005 Summary of contents

  • Page 1

    ... Extended temperature range available DESCRIPTION The DS1005 5-Tap Silicon Delay Line provides five equally spaced taps with delays ranging from 250 ns, with an accuracy 3%, whichever is greater. This device is offered in a standard 14- pin DIP, making it compatible with existing delay line products. Space-saving 8-pin DIPs and 16-pin SOICs are also available ...

  • Page 2

    ... LOGIC DIAGRAM Figure 1 PART NUMBER DELAY TABLE (t PART NO. TAP 1 DS1005- DS1005- DS1005-100 20 ns DS1005-125 25 ns DS1005-150 30 ns DS1005-175 35 ns DS1005-200 40 ns DS1005-250 50 ns Custom delays available , t ) Table 1 PHL PLH TAP 2 TAP ...

  • Page 3

    ... CC TYP MAX UNITS 5. 0 25° ± 5 TYP MAX UNITS ns Table 1 ns Table 1 ns 100 TYP MAX UNITS DS1005 NOTES NOTES 25°C) NOTES ...

  • Page 4

    ... Delay, Rising): The elapsed time between the 1.5V point on the leading edge of the input PLH pulse and the 1.5V point on the leading edge of any tap output pulse. t (Time Delay, Falling): The elapsed time between the 1.5V point on the trailing edge of the input PHL pulse and the 1.5V point on the trailing edge of any tap output pulse DS1005 ...

  • Page 5

    ... TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1005. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each tap is selected and connected to the counter by a VHF switch control unit ...

  • Page 6

    ... TIMING DIAGRAM: SILICON DELAY LINE Figure 2 DALLAS SEMICONDUCTOR TEST CIRCUIT Figure DS1005 ...