AD679 Analog Devices, AD679 Datasheet - Page 4

• Manufacturer Part Number: AD679
• Description: 14-Bit 128 kSPS Complete Sampling ADC
• Manufacturer: Analog Devices

AD679
TIMING SPECIFICATIONS
(All device types T
V
Parameter
SC Delay
Conversion Time
Conversion Rate
Convert Pulse Width
Aperture Delay
Status Delay
Access Time
Float Delay
Output Delay
Format Setup
OE Delay
Read Pulse Width
Conversion Delay
EOCEN Delay
NOTES
1
2
3
4
5
Specifications subject to change without notice.
Model
AD679JN
AD679KN 28-Pin Plastic DIP
AD679JD
AD679KD 28-Pin Ceramic DIP
AD679AD 28-Pin Ceramic DIP
AD679BD 28-Pin Ceramic DIP
AD679SD 28-Pin Ceramic DIP
AD679TD 28-Pin Ceramic DIP
AD679AJ
AD679BJ
AD679SJ
AD679TJ
NOTES
1
2
3
Includes Acquisition Time.
Measured from the falling edge of OE/EOCEN (0.8 V) to the time at which the
C
C
Measured from the rising edge of OE/EOCEN (2.0 V) to the time at which the
For parallel read (14-bits) interface to 16-bit buses, see AD779.
For details grade and package offerings screened in accordance with MIL-STD-
N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.
data lines/EOC cross 2.0 V or 0.8 V. See Figure 4.
output voltage changes by 0.5. See Figure 4; C
883, refer to the Analog Devices Miliary Products Databook or current AD679/
883B data sheet.
DD
OUT
OUT
= +5 V
= 100 pF.
= 50 pF.
2
Package
28-Pin Plastic DIP
28-Pin Ceramic DIP
44-Lead Ceramic JLCC –40 C to +85 C
44-Lead Ceramic JLCC –40 C to +85 C
44-Lead Ceramic JLCC –55 C to +125 C AC
44-Lead Ceramic JLCC –55 C to +125 C AC + DC
5
2, 3
10%)
1
MIN
to T
ORDERING GUIDE
MAX
, V
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SC
C
CR
CP
AD
SD
BA
FD
OD
FS
OE
RP
CD
EO
CC
= +12 V
Temperature
Range
0 C to +70 C
0 C to +70 C
0 C to +70 C
0 C to +70 C
–40 C to +85 C
–40 C to +85 C
–55 C to +125 C AC
–55 C to +125 C AC + DC
OUT
Min
50
0.097
5
0
10
10
10
100
20
195
400
50
= 10 pF.
5%, V
1
EE
Tested
and
Specified
AC
AC + DC
AC
AC + DC
AC
AC + DC
AC
AC + DC
Max
6.3
7.8
3.0
20
400
100
57
80
0
= –12 V
4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
Package
Option
N-28
N-28
D-28
D-28
D-28
D-28
D-28
D-28
J-44
J-44
J-44
J-44
5%,
–4–
3
Figure 4. Load Circuit for Bus Timing Specifications
Figure 1. Conversion Timing
Figure 2. Output Timing
Figure 3. EOC Timing
REV. C