Z8S180 Zilog., Z8S180 Datasheet - Page 104

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

CYC1 CYC0
0
0
1
1
* Calculated interval
0
1
0
1
Table 11. DRAM Refresh Intervals
Refresh Control And RESET
After RESET, based on the initialized value of RCR, refresh cycles occur
with an interval of ten clock cycles and are three clock cycles in duration.
Dynamic Ram Refresh Operation Notes
1. Refresh Cycle insertion is stopped when the CPU is in the following
2. Refresh cycles are suppressed when the bus is released in response to
Insertion
Interval
10 states
20 states
40 states
80 states
states:
–
–
–
–
BUSREQ. However, the refresh timer continues to operate. Thus, the
time at which the first refresh cycle occurs after the Z8X180 re-
acquires the bus depends on the refresh timer and has no timing
relationship with the bus exchange.
During RESET
When the bus is released in response to BUSREQ
During SLEEP mode
During Wait States
10 MHz
(1.0 s)*
(2.0 s)*
(4.0 s)*
(8.0 s)*
8 MHz
(1.25 s)*
(2.5 s)*
(5.0 s)*
(10.0 s)*
Time Interval
6 MHz
1.66 s
3.3 s
6.8 s
13.3 s
M PU Us e r M anual
UM005001-ZMP0400
4 MHz
2.5 s
5.0 s
10.0 s
20.0 s
Z 8018x Fam il y
2.5 MHz
4.0 s
8.0 s
16.0 s
32.0 s
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