Z8S180 Zilog., Z8S180 Datasheet - Page 118

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

Bit
Position Bit/Field
2-0
DMA Register Description
Bit 7
This bit must be set to 1 only when both DMA channels are set to take
their requests from the same device. If this bit is 1 (it resets to 0), the
TEND output of DMA channel o sets a flip-flop, so that thereafter the
device’ s request is visible to channel 1, but not visible to channel 0. The
internal TEND signal of channel 1 clears the FF, so that thereafter, the
device’ s request is visible to channel 0, but no visible to channel 1.
If DMA request are from differing sources, DMA channel 0 request is
forced onto DMA channel 1 after TEND output of DMA channel 0 sets
the flop-flop to alternate.
Bit 6
When both DMA channels are programmed to take their requests from
the same device, this bit (FF mentioned in the previous paragraph)
controls which channel the device’ s request is presented to: 0 = DMA0, 1
= DMA l. When Bit 7 is 1, this bit is automatically toggled by the channel
end output of the channels.
R/W
R/W
Value Description
000
001
010
011
111
DMA1 ext TOUT/DREQ
DMA1 ASCI0
DMA1 ASCI1
DMA1 ESCC
DMA1 PIA27-20 (P1284)
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
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