PALCE20V8 Advanced Micro Devices, PALCE20V8 Datasheet - Page 16

• Manufacturer Part Number: PALCE20V8
• Description: EE CMOS 24-Pin Universal Programmable Array Logic
• Manufacturer: Advanced Micro Devices

POWER-UP RESET
The PALCE20V8 has been designed with the capability
to reset during system power-up. Following power-up,
all flip-flops will be reset to LOW. The output state will be
HIGH independent of the logic polarity. This feature pro-
vides extra flexibility to the designer and is especially
valuable in simplifying state machine initialization. A
timing diagram and parameter table are shown below.
2-182
Parameter
Symbol
AMD
t
t
t
PR
S
WL
Registered
Output
Power
Clock
Parameter Description
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
4 V
Power-Up Reset Waveforms
PALCE20V8 Family
t
PR
Due to the synchronous operation of the power-up reset
and the wide range of ways V
state, two conditions are required to insure a valid
power-up reset. These conditions are:
The V
Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
t
WL
CC
t
S
rise must be monotonic.
Min
Characteristics
CC
See Switching
16491D-16
can rise to its steady
1000
Max
V
CC
Unit
ns