LTC4251 LINER [Linear Technology], LTC4251 Datasheet - Page 11

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LTC4251

Manufacturer Part Number
LTC4251
Description
Negative Voltage Hot Swap Controllers in SOT-23
Manufacturer
LINER [Linear Technology]
Datasheet

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APPLICATIO S I FOR ATIO
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA, and
define an impedance at UV/OV of 30k. In most applica-
tions, 30k impedance coupled with 300mV UV hysteresis
makes the LTC4251/LTC4251-1/LTC4251-2 insensitive to
noise. If more noise immunity is desired, add a 1nF to 10nF
filter capacitor from UV/OV to V
The UV and OV trip point thresholds for the LTC4251-1 are
designed to encompass the standard telecom operating
range of –36V to –72V.
A divider (R1, R2) is used to scale the supply voltage.
Using R1 = 442k and R2 = 34.8k gives a typical operating
range of 33.2V to 81V. The typical under- and overvoltage
shutdown thresholds are then 29.6V and 84.5V. 1%
divider resistors are recommended to preserve threshold
accuracy.
The R1-R2 divider values shown in the Typical Application
set a standing current of slightly more than 100µA, and
define an impedance at UV/OV of 32k. In most applica-
tions, 32k impedance coupled with 260mV UV hysteresis
makes the LTC4251-1 insensitive to noise. If more noise
immunity is desired, add a 1nF to 10nF filter capacitor from
UV/OV to V
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the three
remaining interlock conditions are met.
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load,
but it will not reset the circuit breaker latch. Returning the
supply voltage to an acceptable range restarts the GATE
pin provided all interlock conditions except TIMER are
met.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor, C
TIMER to provide timing for the LTC4251/LTC4251-1/
LTC4251-2. Four different charging and discharging modes
are available at TIMER:
EE
.
U
U
EE
.
W
T
U
, is used at
1. 5.8µA slow charge; initial timing delay
2. 230µA fast charge; circuit breaker delay
3. 5.8µA slow discharge; circuit breaker “cool-off”
4. Low impedance switch; resets capacitor after initial
For initial startup, the 5.8µA pull-up is used. The low
impedance switch is turned off and the 5.8µA current
source is enabled when the four interlock conditions are
met. C
When C
turns on and discharges C
and the load turns on.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than 50mV across R
TIMER pin charges C
GATE pin pulls low and the LTC4251/LTC4251-1/
LTC4251-2 latch off. The part remains latched off until
either the UV/OV pin is momentarily pulsed low, or V
dips into UVLO and is then restored. The circuit breaker
timeout period is given by
Intermittent overloads may exceed the 50mV threshold at
SENSE, but if their duration is sufficiently short TIMER will
not reach 4V and the LTC4251/LTC4251-1/LTC4251-2
will not latch off. To handle this situation, the TIMER
discharges C
SENSE voltage is less than 50mV. Therefore any intermit-
tent overload with an aggregate duty cycle of 2.5% or more
will eventually trip the circuit breaker and latch off the
LTC4251/LTC4251-1/LTC4251-2. Figure 3 shows the cir-
cuit breaker response time in seconds normalized to 1µF.
The asymmetric charging and discharging of C
gauge of MOSFET heating.
timing delay, in undervoltage lockout, and in overvolt-
age
t
t
=
=
4
4
T
230
5 8
T
V C
V C
charges to 4V in a time period given by:
.
reaches 4V (V
µ
µ
A
A
T
T
T
slowly with a 5.8µA pull-down whenever the
LTC4251/LTC4251-1/
T
with 230µA. If C
TMRH
T
. The GATE output is enabled
), the low impedance switch
LTC4251-2
T
charges to 4V, the
T
is a fair
11
(1)
(2)
425112fa
S
, the
IN

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