LTC4251 LINER [Linear Technology], LTC4251 Datasheet - Page 7

• Manufacturer Part Number: LTC4251
• Description: Negative Voltage Hot Swap Controllers in SOT-23
• Manufacturer: LINER [Linear Technology]

PI FU CTIO S
references in the text to overvoltage, OV, V
SENSE (Pin 1): Circuit Breaker/Current Limit SENSE Pin.
Load current is monitored by sense resistor R
between SENSE and V
SENSE exceeds V
tor activates a 230µA TIMER pin pull-up current. The
LTC4251/LTC4251-1/LTC4251-2 latch off when C
to 4V. If SENSE exceeds V
limit amplifier pulls GATE down and regulates the MOSFET
current at V
circuit, SENSE may overshoot 100mV. If SENSE reaches
V
GATE low with a strong pull-down. To disable the circuit
breaker and current limit functions, connect SENSE to V
Kelvin-sense connections between the sense resistor and
the V
Figure 6.
V
pin to the negative side of the power supply.
V
positive side of the supply through a dropping resistor. A
shunt regulator typically clamps V
undervoltage lockout (UVLO) circuit holds GATE low until
the V
If UV is high, OV is low and V
starts an initial timing cycle before initiating a GATE ramp
up. If V
immediately.
TIMER (Pin 4): Timer Input. TIMER is used to generate a
delay at start up, and to delay shutdown in the event of an
output overload. TIMER starts an initial timing cycle when
the following conditions are met: UV is high, OV is low, V
clears UVLO, TIMER pin is low, GATE is lower than V
and V
charges C
V
pulls low and GATE is activated.
FCL
EE
IN
TMRH
U
(Pin 3): Positive Supply Input. Connect this pin to the
(Pin 2): Negative Supply Voltage Input. Connect this
IN
EE
(200mV), the fast current limit comparator pulls
SENSE
IN
pin is greater than V
(4V) the timing cycle terminates, TIMER quickly
and SENSE pins are strongly recommended, see
drops below approximately 8.2V, GATE pulls low
T
U
, generating a time delay. If C
ACL
– V
/R
EE
CB
S
< V
. In the event of a catastrophic short-
(50mV), the circuit breaker compara-
U
CB
EE
. A pull-up current of 5.8µA then
, and controlled in three steps. If
ACL
UV/OV refers to the UV pin for the LTC4251-2. The OV comparator in the LTC4251-2 is disabled. All
LKO
IN
(100mV), the analog current
comes out of UVLO, TIMER
(9.2V), overriding UV/OV.
IN
OVHI
at 13V. An internal
and V
T
S
charges to
connected
OVLO
T
charges
do not apply to the LTC4251-2.
GATEL
EE
IN
.
If SENSE exceeds 50mV while GATE is high, a 230µA pull-
up current charges C
TIMER reaches 4V, a 5.8µA pull-down current slowly
discharges C
to the 4V V
5.8µA pull-up source and GATE quickly pulls low. The
LTC4251/LTC4251-1/LTC4251-2 fault latches may be
cleared by either pulling TIMER low with an external
device, or by pulling UV/OV below V
UV/OV (Pin 5): Undervoltage/Overvoltage Input. This dual
function pin detects undervoltage as well as overvoltage.
The high threshold at the UV comparator is set at V
with V
comparator is set at V
UV/OV < V
UV/OV > V
LTC4251-1/LTC4251-2 attempt to start-up. The internal
UVLO at V
an internal fault latch. A high at OV pulls GATE low but does
not reset the fault latch. A 1nF to 10nF capacitor at UV/OV
eliminates transients and switching noise from affecting
the UV/OV thresholds and prevents glitches at the GATE
pin.
GATE (Pin 6): N-Channel MOSFET Gate Drive Output. This
pin is pulled high by a 58µA current source. GATE is pulled
low by invalid conditions at V
latch. GATE is actively servoed to control fault current as
measured at SENSE. A compensation capacitor at GATE
stabilizes this loop. A comparator monitors GATE to
ensure that it is low before allowing an initial timing cycle,
GATE ramp up after an overvoltage event, or restart after
a current limit fault.
UVHST
IN
UVLO
TMRH
UVHI
T
always overrides UV/OV. A low at UV resets
hysteresis. The high threshold at the OV
. In the event that C
LTC4251/LTC4251-1/
or UV/OV > V
and UV/OV < V
threshold, TIMER latches high with a
T
. If SENSE drops below 50mV before
OVHI
IN
with V
(UVLO), UV/OV, or the fault
OVHI
T
eventually integrates up
OVLO
LTC4251-2
, GATE pulls low. If
UVLO
OVHST
, the LTC4251/
.
hysteresis. If
425112fa
UVHI
7