LTC4425EDD LINER [Linear Technology], LTC4425EDD Datasheet - Page 7

• Manufacturer Part Number: LTC4425EDD
• Description: Linear SuperCap Charger with Current-Limited Ideal Diode and V/I Monitor
• Manufacturer: LINER [Linear Technology]

PIN FUNCTIONS
V
nects to the top of the 2-cell supercap stack.
PROG (Pin 3): Charge Current Program and Charge
Current Monitor Pin. A resistor connected from PROG to
ground programs the charge current. In LDO mode, this
pin always servos to 1V. However, if the charge current
profi le is turned on, this pin servos to a voltage between
1V and 0.1V depending on the input-to-output differential.
In all cases, the voltage on this pin always represents the
actual charge current.
SEL (Pin 4): Logic Input to Select One of the Two Possible
Clamp Voltages (V
maximum voltage across any supercap of the stack is
2.45V. If the pin is a logic high, it is 2.7V. Do not fl oat
this pin.
FB (Pin 5): In LDO mode, output voltage is programmed
by a resistor divider from V
mode, the voltage on this pin always servos to the internal
reference voltage of 1.2V. If the FB pin is pulled up to V
the LDO mode is disabled and the charge current profi le
mode is turned on. Do not fl oat this pin.
EN (Pin 6): Digital Input to Enable the Charger. If this pin
is a logic high, the part is enabled and it draws only 20μA
of quiescent current from the input or output when idle.
If this pin is a logic low, the part is in shutdown mode and
draws less than 2μA. Do not fl oat this pin.
PFI_RET (Pin 7): This pin connects to the bottom of the
external resistor divider for the input power-fail compara-
tor. In shutdown mode, an internal switch opens up this
path to reduce the current drawn by the resistor divider.
OUT
(Pin 1, 2): Output Pin of the Charger. Typically con-
CLAMP
). If the pin is a logic low, the
OUT
via the FB pin. In this
IN
,
PFO (Pin 8): Open Drain Output of the Power-Fail Com-
parator. This pin is driven to logic low if at least one of the
following conditions is true: (1) V
programmed by an external divider via PFI, (2) V
not reached within 7.5% of its fi nal programmed value
in LDO mode, or (3) V
charge current profi le mode. When all these conditions
are false for at least 200ms, this pin goes high impedance
indicating that power is good.
PFI (Pin 9): Input to the Power-Fail Comparator. The input
voltage below which PFO pin indicates a power-fail condi-
tion can be programmed by connecting this pin to an
external resistor divider between V
V
supercap stack. An internal leakage balancing amplifi er
drives this pin to a voltage which is exactly half of V
V
a DC source like a Li-Ion/Polymer battery or a USB port.
GND (Exposed Pad Pin 13): GND. The Exposed Pad should
be connected to a continuous ground plane on the second
layer of the printed circuit board by several vias directly
under the part to achieve optimum thermal conduction.
MID
IN
(Pin 11, 12): Input Power Pin. Typically connected to
(Pin 10): Connects to the Midpoint of the 2-Cell
OUT
is not within 250mV of V
IN
IN
is less than a value
and PFI_RET pin.
LTC4425
OUT
OUT
IN
7
4425p
has
in
.