CY7B923-400JI CYPRESS [Cypress Semiconductor], CY7B923-400JI Datasheet
CY7B923-400JI
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CY7B923-400JI Summary of contents
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... Built-In Self-Test • Single +5V supply • 28-pin SOIC/PLCC/LCC • 0.8 BiCMOS Functional Description The CY7B923 HOTLink™ Transmitter and CY7B933 HOTLink Receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and CY7B923 Transmitter Logic Block Diagram SC/D (D ...
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... HOST CY7B923 Transmitter Pin Configurations SOIC Top View OUTB 1 28 OUTC 2 27 OUTC CCN BISTEN 5 24 GND 6 23 MODE 7 22 7B923 CCQ 9 20 SVS ...
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... Power Applied Supply Voltage to Ground Potential DC Input Voltage Output Current into TTL Outputs (LOW)...................... 30 mA Output Current into PECL outputs (HIGH) Pin Descriptions CY7B923 HOTLink Transmitter Name I/O Description D TTL In Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW ...
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... CY7B923 HOTLink Transmitter (continued) Name I/O Description OUTA PECL Out Differential Serial Data Outputs. These PECL 100K outputs (+5V referenced) are capable of driving OUTB terminated transmission lines or commercial fiber optic transmitter modules. Unused pairs of outputs OUTC can be wired to V level on FOTO, and will remain at their “logical zero” states when FOTO is asserted. OUTC is unaffected by the level on FOTO ...
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... V Power for internal circuitry. CCQ GND Ground. CY7B923 HOTLink Transmitter Block Diagram Description Input Register The Input register holds the data to be processed by the HOT- Link transmitter and allows the input timing to be made consis- tent with standard FIFOs. The Input register is clocked by CKW ...
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... Test logic includes the initialization and control for the Built-In Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic to properly select the data encod- ing. Test logic is discussed in more detail in the CY7B923 HOTLink Transmitter Operating Mode Description ...
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... Test logic includes the initialization and control for the Built-In Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic for the decoder. Test logic is dis- cussed in more detail in the CY7B933 HOTLink Receiver Op- erating Mode Description 7 CY7B923 CY7B933 , SC/D, and 0 7 ...
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... CY7B923/CY7B933 Electrical Characteristics Parameter Description TTL OUTs, CY7B923: RP; CY7B933 Output HIGH Voltage OHT V Output LOW Voltage OLT I Output Short Circuit Current OST TTL INs, CY7B923 SC/D, SVS, ENA, ENN, CKW, FOTO, BISTEN; CY7B933: RF, REFCLK, BISTEN Input HIGH Voltage IHT V Input LOW Voltage ...
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... B [12 [7] [7] [7, 13] [7, 14] and t minimum timing assures correct data load on rising edge of CKW, but not RP function or timing pF. L 2.0V, over the operating range CY7B923 CY7B933 Max. Unit = 5. = < (Includes fixture and ...
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... B B [17, 18 0.1 +0.1 6.5 6.5 20 100 0.9t 0.9t B /10 if data is being received. See note. CKW , SC/D, and RVS) are loaded with similar DC and AC loads and V specification (approximately CY7B923 CY7B933 7B933 7B933-400 Max. Min. Max. Unit 3.03 6.25 2.5 6. ...
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... Switching Waveforms for the CY7B923 HOTLink Transmitter CKW ENA D – SC/D, SVS, BISTEN RP t CPWL CKW ENN D – SC/D, SVS, BISTEN t CPWL t SENP t t HENP SD 10,11 NOTES VALID DATA PDF t PDR t PPWH t CKW t CPWH CY7B923 CY7B933 t CKW t CPWH ...
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... Static Alignment INA , INB SAMPLE WINDOW t CKR t CPRL PRF t CKX CPXL t CPXH 1.5V B923–15 Error-F ree Window INA INB B923–16 12 CY7B923 CY7B933 t ROH B923–13 B923–14 t EFW t B BIT CENTER BIT CENTER B923–17 ...
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... Mbytes per second for -400 devices) over sev- eral types of serial interface media. Figure 2 illustrates the flow of data through the HOTLink CY7B923 transmitter pipeline. Data is latched into the transmitter on the rising edge of CKW when enabled by ENA or ENN asserted LOW with a 60% LOW/40% HIGH duty cycle when ENA is LOW ...
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... HOTLink Transmitter and Receiver interface to fiber op- tic and copper media. More information on interfacing HOTLink to various media can be found in the HOTLink Design Considerations application note. CY7B923 HOTLink Transmitter Operating Mode Description In normal operation, the Transmitter can operate in either of two modes. The Encoded mode allows a user to send and ...
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... An internal voltage comparator detects when an output differential pair is wired to V source for that pair to be disabled. This results in a power savings of around 5 mA for each unused pair. 15 CY7B923 CY7B933 CLOCKED FIFO 7C44X/ ...
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... Random Jitter (R while sending a continuous K28.7 (C7.0). Transmitter Test Mode Description The CY7B923 Transmitter offers two types of test mode oper- ation, BIST mode and Test mode normal system applica- tion, the Built-In Self-Test (BIST) mode can be used to check the functionality of the Transmitter, the Receiver, and the link connecting them ...
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... ENN HIGH and resume normal function. Note: It may be advisable to send violation characters to test the RVS output in the Receiver. This can be done by explicitly sending a violation with the SVS input, or allowing the trans- 17 CY7B923 CY7B933 CY7B923 OUTA OUTB OUTC CY7B933 SO DON'T CARE INA ...
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... HOTLink. This data can use any encoding method suitable to the designer. The only restrictions upon the data encod- ing method is that it contain suitable transition density for the Receiv- 18 CY7B923 CY7B933 context control bit (SC/D), and a system ...
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... As a result of the receiver’s wide jitter tolerance, valid data will appear at the receiv- er’s outputs a few byte times after a worst-case phase change. 19 CY7B923 CY7B933 RVS SC/D Qouts Name ...
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... G and g, and H and h. Bits i and j are derived, respec- tively, from (A,B,C,D,E) and (F,G,H). The bit labeled A in the description of the 8B/10B Transmission Code corresponds to bit 0 in the numbering scheme of the FC-2 specification, B corresponds to bit 1, as shown below. FC-2 bit designation— HOTLink D/Q designation— 7 8B/10B bit designation— 20 CY7B923 CY7B933 , 0 ...
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... It is also positive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is 0011. 2. Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones also 21 CY7B923 CY7B933 ...
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... Transmission Char- acter in which the error occurred. Table 2 shows an example of this behavior. Character RD Character D21.1 D10.2 101010 1001 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 22 CY7B923 CY7B933 Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... Code Rule Violation and SVS Tx Pattern 111 00000 100111 1000 111 00001 001111 1010 111 00010 110000 0101 Running Disparity Violation Pattern 111 00100 110111 0101 31 CY7B923 CY7B933 Current RD+ fghj abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 ...
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... Ordering Information Speed Ordering Code Standard CY7B923-JC CY7B923-JI CY7B923-SC CY7B923-LMB 400 CY7B923-400JC CY7B923-400JI 155 CY7B923-155JC CY7B923-155JI Speed Ordering Code Package Name Standard CY7B933-JC CY7B933-JI CY7B933-SC CY7B933-LMB 400 CY7B933-400JC CY7B933-400JI 155 CY7B933-155JC CY7B933-155JI Notes: 29. C1.7 = Transmit Negative K28.5 ( K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C1.7 if K28.5 is received with RD+, otherwise K28 ...
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... FALL t 9, 10, 11 CKR t 9, 10, 11 CPRH t 9, 10, 11 CPRL 10, 11 PRF t 9, 10, 11 PRH 10, 11 ROH 10, 11 CKX t 9, 10, 11 CPXH t 9, 10, 11 CPXL Document #: 38 00189 I 33 CY7B923 CY7B933 ...
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... Package Diagrams 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 34 CY7B923 CY7B933 51-85001-A 51-80051 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOIC S21 CY7B923 CY7B933 51-85026-A ...