CY7B923-SC Cypress Semiconductor Corp, CY7B923-SC Datasheet
CY7B923-SC
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CY7B923-SC Summary of contents
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... Cypress Semiconductor Corporation Document #: 38-02017 Rev. *C HOTLink Transmitter/Receiver Functional Description The CY7B923 HOTLink Receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and twisted pair). Standard HOTLink data rates range from 160-330 Mbits/second. Higher speed HOTLink is also ...
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... HOST CY7B923 Transmitter Pin Configurations SOIC Top View OUTB 1 OUTC 2 OUTC CCN BISTEN 5 GND 6 MODE 7 7B923 CCQ SVS PLCC/LCC Top View 2726 28 BISTEN 5 GND 6 MODE 7 7B923 CCQ SVS 1213 14 15 1718 Document #: 38-02017 Rev. *C SERIAL LINK Figure 1. HOTLink System Connections CY7B933 Receiver Pin Configurations ...
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... Pin Descriptions CY7B923 HOTLink Transmitter Name I/O Description D TTL In Parallel Data Input. Data is clocked into the Transmitter on the rising edge of CKW if ENA is LOW (or on the next rising CKW with ENN LOW). If ENA and ENN are HIGH, a Null character (K28. sent. When MODE is HIGH, D ...
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... CY7B923 HOTLink Transmitter (continued) Name I/O Description RP TTL Out Read Pulse 60% LOW duty-cycle byte-rate pulse train suitable for the read pulse in CY7C42X FIFOs. The frequency the same as CKW when enabled by ENA, and duty cycle is independent of the CKW duty cycle. Pulse widths are set by logic internal to the transmitter. In BIST mode, RP will remain HIGH for all but the last byte of a test loop ...
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... V Power for internal circuitry. CCQ GND Ground. CY7B923 HOTLink Transmitter Block Diagram Description Input Register The Input register holds the data to be processed by the HOTLink transmitter and allows the input timing to be made consistent with standard FIFOs. The Input register is clocked by CKW and loaded with information on the D SVS pins ...
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... Test logic includes the initialization and control for the Built-In Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic to properly select the data encoding. Test logic is discussed in more detail in the CY7B923 HOTLink Transmitter Operating Mode Description. CY7B933 HOTLink Receiver Block Diagram Description Serial Data Inputs Two pairs of differential line receivers are the inputs for the serial data stream. INA± ...
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... Mbytes per second (40 Mbytes per second for –400 devices) over several types of serial interface media. Figure 7 illustrates the flow of data through the HOTLink CY7B923 transmitter pipeline. Data is latched into the transmitter on the rising edge of CKW when enabled by ENA or ENN asserted LOW with a 60% LOW/40% HIGH duty cycle when ENA is LOW ...
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... More information on interfacing HOTLink to various media can be found in the HOTLink Design Considerations application note. CY7B923 HOTLink Transmitter Operating Mode Description In normal operation, the Transmitter can operate in either of two modes. The Encoded mode allows a user to send and receive eight-bit data and control information without first converting it to transmission characters ...
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... HIGH), the Encoder will insert a pad character K28.5 (e.g., C5.0) to maintain proper link synchronization (in Bypass = 111 00000 and SC/D 7-0 CLOCKED FIFO 7C44X/5X ENR CKR ENN CKW D ,SC 7B923 HOTLINK TRANSMIT TER HOTLINK RECEIVER 7B933 CKR RDY Q ,SC CKW ENW 7C44X/5X CLOCKED FIFO CY7B923 CY7B933 B923–21 Page ...
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... K28.7 (C7.0). Transmitter Test Mode Description The CY7B923 Transmitter offers two types of test mode operation, BIST mode and Test mode normal system application, the Built-In Self-Test (BIST) mode can be used to check the functionality of the Transmitter, the Receiver, and the link connecting them ...
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... IB IB– (Qa) (Qb) (Qc) (Qd (Qe) IA (Qi) IA– (Qf) (Qg) (Qh) (Qj) GND Figure 5. HOTLink Connection Diagram CY7B923 CY7B933 .01UF VCC 130 Fiber Optic Fiber Tx TX TX+ TX– 130 GND Coax or Twisted Pair A B 270 270 .01UF 649 1500 RL/2 Coax or Twisted Pair RL/2 Optional Signal Det ...
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... SVS input, or allowing the trans- mitter BIST loop to run while the Receiver runs in normal mode. The BIST loop includes deliberate violation symbols and will adequately test the RVS function. CY7B923 CY7B933 CY7B923 OUTA OUTB OUTC CY7B933 SO DON’T CARE ...
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... The only restrictions upon the data encoding method is that it contain suitable transition density for the Receiver PLL data synchronizer (one per 10 bit byte) and that it be compatible with the transmission media. CY7B923 CY7B933 – context control bit (SC/D), and ...
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... Note: Acquisition time is measured from worst-case phase or frequency change to zero phase and frequency error result of the receiver’s wide jitter tolerance, valid data will appear at the receiver’s outputs a few byte times after a worst-case phase change. CY7B923 CY7B933 RVS SC/D Qouts Name 0 1 00-0B C0 ...
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... The bit labeled A in the description of the 8B/10B Transmission Code corresponds to bit 0 in the numbering scheme of the FC-2 specification, B corresponds to bit 1, as shown below. FC-2 bit designation— HOTLink D/Q designation— 8B/10B bit designation— CY7B923 CY7B933 , 0 Page ...
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... It is also pos- itive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is 0011. 2. Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones also CY7B923 CY7B933 Page ...
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... Transmission Character in which the error occurred. Table 2 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CY7B923 CY7B933 Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 02 ...
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... D0.2 010 00000 100111 100001 1011 D1.2 010 00001 011101 010100 1011 D2.2 010 00010 101101 011000 1001 D3.2 010 00011 110001 100010 1001 CY7B923 CY7B933 (continued) Bits Current RD Current RD+ EDC- BA abcdei fghj abcdei 1001 010010 1001 110001 1001 001010 ...
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... D6.4 100 00110 011001 001010 1100 D7.4 100 00111 111000 101001 0011 D8.4 100 01000 111001 011001 0011 D9.4 100 01001 100101 CY7B923 CY7B933 (continued) Bits Current RD Current RD+ EDC- BA abcdei fghj abcdei 1100 000111 0011 000110 1100 100101 ...
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... D12.6 110 01100 001101 010101 1010 D13.6 110 01101 101100 110100 1010 D14.6 110 01110 011100 001101 1010 D15.6 110 01111 010111 CY7B923 CY7B933 (continued) Bits Current RD Current RD+ EDC- BA abcdei fghj abcdei 1010 101100 1010 011100 1010 101000 ...
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... CY7B923 CY7B933 (continued) Bits Current RD Current RD+ EDC- BA abcdei fghj abcdei 1110 110010 0111 001011 1110 101010 1110 011010 0001 000101 ...
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... Code Rule Violation and SVS Tx Pattern 111 00000 100111 111 00001 001111 111 00010 110000 Running Disparity Violation Pattern 111 00100 110111 CY7B923 CY7B933 Current RD+ fghj abcdei fghj 0100 110000 1011 1001 110000 0110 0101 110000 1010 0011 110000 ...
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... Supply Voltage to Ground Potential ............... –0.5V to +7.0V DC Input Voltage............................................ –0.5V to +7.0V Output Current into TTL Outputs (LOW) ......................30 mA Output Current into PECL Outputs (HIGH) ................–50 mA CY7B923/CY7B933 Electrical Characteristics Parameter Description TTL OUTs, CY7B923: RP; CY7B933 Output HIGH Voltage OHT V Output LOW Voltage OLT ...
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... CY7B923/CY7B933 Electrical Characteristics Parameter Description Miscellaneous [11] I Transmitter Power Supply CCT Current [12] I Receiver Power Supply CCR Current [13] Capacitance Parameter Description C Input Capacitance IN AC Test Loads and Waveforms OUTPUT R 1= 910 510 L C < (Includes fixture and probe capacitance) (a) TTL AC Test Load 3 ...
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... –3 5t – –2.5 t –2 –3 5t – –3 4t – – – –2.5 t –2 –3 2t – +0.1 –0.1 +0.1 –0 pF. L 1.35V). The TTL switching threshold is 1.5V. CC CY7B923 CY7B933 Max Unit 62 1 175 Max. Unit + +0.1 % Page ...
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... REFCLK Clock Pulse HIGH CPXH t REFCLK Clock Pulse LOW CPXL t Propagation Delay (note PECL and TTL DS [26] thresholds) [13, 27] t Static Alignment SA [13, 28] t Error Free Window EFW Switching Waveforms for the CY7B923 HOTLink Transmitter CKW ENA D – SC/D, SVS, BISTEN RP CKW ENN D – ...
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... Switching W0aveforms for the CY7B933 HOTLink Receiver CKR RDY SC/D,RVS, REFCLK NOTE SO Static Alignment INA , INB SAMPLE WINDOW Document #: 38-02017 Rev CPRH t CPRL t PRH t PRF CPXL t CPXH t DS 1.5V Error-free Window CKR ROH t CKX t EFW INA INB t B BIT CENTER BIT CENTER CY7B923 CY7B933 Page ...
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... DATA LATCHED IN CKW ENA D0 7, SC/D, DATA SVS RP OUTX Ordering Information Speed Ordering Code Standard CY7B923-JC CY7B923-JI CY7B923-SC 400 CY7B923-400JC CY7B923-400JI 155 CY7B923-155JC CY7B923-155JI Standard CY7B933-JC CY7B933-JI CY7B933-SC 400 CY7B933-400JC CY7B933-400JI 155 CY7B933-155JC CY7B933-155JI Notes: 29. C1.7 = Transmit Negative K28.5 (–K28.5+) disregarding Current RD. ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-lead Plastic Leaded Chip Carrier J64 28-lead (300-mil) Molded SOIC S21 CY7B923 CY7B933 51-85001-A 51-85026-A ...
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... Changed OUTA± pin description to improve consistency with diagram. Changed INA± pin description to include what to do with unused pairs of inputs. Changed Equation in note 6–old one made no sense. BSS Changed Hotlink Transmitter/Receiver to Hotlink Transmitter/Receiver. OOR Removed all references to Military parts (Obsolete): CY7B923-LMB, CY7B933-LMB Description of Change CY7B923 CY7B933 Page ...