CY7B923-SC Cypress Semiconductor Corp, CY7B923-SC Datasheet - Page 15

• Manufacturer Part Number: CY7B923-SC
• Description: TRANSMITTER HOTLINK 28-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink™r
• Type: Transmitter and Receiverr

Specifications of CY7B923-SC

• Protocol: Fibre Channel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 428-1299

Document #: 38-02017 Rev. *C
Receiver Test Mode Description
The CY7B933 Receiver offers two types of test mode
operation, BIST mode and Test mode. In a normal system
application, the Built-In Self-Test (BIST) mode can be used to
check the functionality of the Transmitter, the Receiver and the
link connecting them. This mode is available with minimal
impact on user system logic, and can be used as part of the
normal system diagnostics. Typical connections and timing
are shown in Figure 6.
BIST Mode
BIST Mode function is as follows:
Note: A specific test of the RVS output may be required to
assure an adequate test. To perform this test, it is only
necessary to have the Transmitter send violation (SVS =
HIGH) for a few bytes before beginning the BIST test
sequence. Alternatively, the Receiver could enter BIST mode
after the Transmitter has begun sending BIST loop data, or be
removed before the Transmitter finishes sending BIST loops,
each of which contain several deliberate violations and should
cause RVS to pulse HIGH.
BIST mode is intended to check the entire function of the
Transmitter, serial link, and Receiver. It augments normal
factory ATE testing and provides the user system with a
rigorous test mechanism to check the link transmission
system, without requiring any significant system overhead.
When in Bypass mode, the BIST logic will function in the same
way as in the Encoded mode. MODE = HIGH and BISTEN =
LOW causes the Receiver to switch to Encoded mode and begin
checking the decoded received data of the BIST pattern, as if
MODE = LOW. When BISTEN returns to HIGH, the Receiver
resumes normal Bypass operation. In Test mode the BIST function
works as in the normal mode.
Test Mode
The MODE input pin selects between three receiver functional
modes. When wired to VCC, the Shifter contents bypass the
Decoder and go directly from the Decoder latch to the Q
the Output latch. When wired to GND, the outputs are decoded
using the 8B/10B codes shown at the end of this datasheet and
become Q
used for factory or incoming device test. This mode can be selected
by leaving the MODE pin open (internal circuitry forces the open pin
to VCC/2).
Test mode causes the Receiver to function in its Encoded
mode, but with INB (INB+) as the bit rate Test clock instead of
the Internal PLL generated bit clock. In this mode, transfers
between the Shifter, Decoder register and Output register are
controlled by their normal logic, but with an external bit rate
clock instead of the PLL (the recovered bit clock). Internal logic
1. Set BISTEN LOW to enable self-test generation and await
2. Monitor RVS and check for any byte time with the pin HIGH
3. When testing is completed, set BISTEN HIGH and resume
RDY LOW indicating that the initialization code has been
received.
to detect pattern mismatches. RDY will pulse HIGH once
per BIST loop, and can be used by an external counter to
monitor test pattern progress. Q
expected pattern and may be useful for debug purposes.
normal function.
0-7
, RVS, and SC/D. The third function is Test mode,
0-7
and SC/D will show the
a-j
inputs of
and test pattern inputs can be synchronized by sending a
SYNC pattern and allowing the Framer to align the logic to the
bit stream. The flow is as follows:
(While in Test mode and in BIST mode with RF HIGH, the Q
RVS, and SC/D outputs reflect various internal logic states and not
the received data.)
Test mode is intended to allow logical, DC, and AC testing of
the Receiver without requiring that the tester generate input
data at the bit rate or accommodate the PLL lock, tracking and
frequency range characteristics that are required when the
part operates in its normal mode.
X3.230 Codes and Notation Conventions
Information to be transmitted over a serial link is encoded eight
bits at a time into a 10-bit Transmission Character and then
sent serially, bit by bit. Information received over a serial link
is collected ten bits at a time, and those Transmission
Characters that are used for data (Data Characters) are
decoded into the correct eight-bit codes. The 10-bit Trans-
mission Code supports all 256 8-bit combinations. Some of the
remaining Transmission Characters (Special Characters) are
used for functions other than data transmission.
The primary rationale for use of a Transmission Code is to
improve the transmission characteristics of a serial link. The
encoding defined by the Transmission Code ensures that suffi-
cient transitions are present in the serial bit stream to make
clock recovery possible at the Receiver. Such encoding also
greatly increases the likelihood of detecting any single or
multiple bit errors that may occur during transmission and
reception of information. In addition, some Special Characters
of the Transmission Code selected by Fibre Channel Standard
consist of a distinct and easily recognizable bit pattern (the
Special Character Comma) that assists a Receiver in
achieving word alignment on the incoming bit stream.
Notation Conventions
The documentation for the 8B/10B Transmission Code uses
letter notation for the bits in an 8-bit byte. Fibre Channel
Standard notation uses a bit notation of A, B, C, D, E, F, G, H
for the 8-bit byte for the raw 8-bit data, and the letters a, b, c,
d, e, i, f, g, h, j for encoded 10-bit data. There is a correspon-
dence between bit A and bit a, B and b, C and c, D and d, E
and e, F and f, G and g, and H and h. Bits i and j are derived,
respectively, from (A,B,C,D,E) and (F,G,H).
The bit labeled A in the description of the 8B/10B Transmission
Code corresponds to bit 0 in the numbering scheme of the
FC-2 specification, B corresponds to bit 1, as shown below.
1. Assert Test mode for several test clock cycles to establish
2. Assert RF to enable reframing.
3. Input a repeating sequence of bits representing K28.5
4. RDY falling shows the byte boundary established by the
5. Proceed with pattern, voltage and timing tests as is conve-
normal counter sequence.
(Sync).
K28.5 input pattern.
nient for the test program and tester to be used.
FC-2 bit designation—
HOTLink D/Q designation— 7 6 5 4 3 2 1 0
8B/10B bit designation—
7 6 5 4 3 2 1 0
H G F E D C B A
CY7B923
CY7B933
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