PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet
PI7C21P100NH
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PI7C21P100NH Summary of contents
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PI7C21P100 2-PORT PCI-X BRIDGE REVISION 1.06 3545 NORTH FIRST STREET SAN JOSE, CA 95134 PH: 1-877-PERICOM (1-877-737-4266) FAX: 1-408-435-1100 EMAIL: SOLUTIONS@PERICOM.COM INTERNET: HTTP://WWW.PERICOM.COM ...
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LIFE SUPPORT POLICY Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of ...
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REVISION HISTORY Date Revision Number 12/04/03 1.00 First Release of Data Sheet 12/11/03 1.01 01/22/04 1.02 02/02/04 1.03 Corrected Device ID Register bits 11:0 descriptions. 03/15/04 1.04 Corrected pin designation for P_RST to E22 in section 3.2.1 09/13/04 1.05 Corrected ...
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This page intentionally left blank. 2-PORT PCI-X BRIDGE ADVANCE INFORMATION Page June 10, 2005 Revision 1.06 PI7C21P100 ...
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TABLE OF CONTENTS 1 DESCRIPTION................................................................................................................................... 9 2 FEATURES ......................................................................................................................................... 9 3 SIGNAL DEFINITIONS.................................................................................................................. 10 3.1 SIGNAL TYPES ....................................................................................................................... 10 3.2 SIGNALS .................................................................................................................................. 10 3.2.1 PRIMARY BUS INTERFACE SIGNALS............................................................................... 10 3.2.2 PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION.......................................... 12 3.2.3 SECONDARY ...
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PRIMARY AND SECONDARY CLOCK INPUTS ................................................................. 34 6.2 CLOCK JITTER........................................................................................................................ 34 6.3 MODE AND CLOCK FREQUENCY DETERMINATION ..................................................... 34 6.3.1 PRIMARY BUS ..................................................................................................................... 34 6.3.2 SECONDARY BUS ............................................................................................................... 35 6.3.3 CLOCK STABILITY.............................................................................................................. 36 6.3.4 DRIVER IMPEDANCE SELECTION................................................................................... 36 7 ...
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MISCELLANEOUS CONTROL REGISTER – OFFSET 44h........................................... 52 8.1.37 EXTENDED CHIP CONTROL REGISTER 1 – OFFSET 48h......................................... 52 8.1.38 EXTENDED CHIP CONTROL REGISTER 2 – OFFSET 48h......................................... 53 8.1.39 ARBITER MODE REGISTER – OFFSET 50h................................................................. 53 8.1.40 ARBITER ENABLE REGISTER ...
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LIST OF TABLES T 3-1 PIN LIST 304-PIN PBGA........................................................................................................... 19 ABLE T 4-1 PCI AND PCI-X TRANSACTIONS .......................................................................................... 22 ABLE T 4-2 WRITE TRANSACTION FORWARDING ............................................................................... 23 ABLE T 4-3 READ TRANSACTIN HANDLING.......................................................................................... 25 ABLE T 4-4 DEVICE NUMBER TO ...
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DESCRIPTION The PI7C21P100 is a 2-port PCI-X 2.0 Bridge designed to be compliant with the PCI-X Addendum to the Local Bus Specification Revision 1.0a. The PI7C21P100 is able to handle 64-bit data at a maximum bus frequency of 133MHz. ...
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SIGNAL DEFINITIONS 3.1 SIGNAL TYPES Signal Type STS 3.2 SIGNALS Signal names that end with “#” are active LOW. 3.2.1 PRIMARY BUS INTERFACE SIGNALS Name Pin # P_AD[31:0] J23, M21, M22, L21, ...
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Name Pin # P_TRDY# B15 P_DEVSEL# D21 P_STOP# C4 P_LOCK# C14 P_IDSEL B19 P_PERR# C8 P_SERR# B4 P_REQ# B21 P_GNT# C20 P_RST# E22 Page 2-PORT PCI-X BRIDGE ADVANCE INFORMATION Type Description STS Primary TRDY (Active LOW). Driven ...
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PRIMARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION Name Pin # P_AD[63:32] B11, D10, C10, A4, B10, C9, B9, A3, B8, B3, C7, B7, D6, B6, B5, C2, D2, F4, E3, F3, B1, F2, G3, H3, H2, E1, J3, G1, ...
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SECONDARY BUS INTERFACE SIGNALS Name Pin # S_AD[31:0] N22, N21, P22, P21, M23, P20, N23, R22, T23, R21, W23, T22, U22, U21, V22, V21, W21, V20, AA20, AB18, Y18, AA16, AB15, AC17, AA13, AA12, AC15, AB11, AC11, AC9, AB9, ...
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Name Pin # S_SERR# AB19 S_REQ[6:2]# AC3, AB5, AB3, W2, AA2 S_REQ[1]# AA23 S_GNT[6:2]# AC4, AB4, AC5, Y2, AB1 S_GNT[1]# AA19 S_RST# U23 3.2.4 SECONDARY BUS INTERFACE SIGNALS – 64-BIT EXTENSION Name Pin # S_AD[63:32] AB8, AB7, AA7, AB6, AA6, ...
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Name Pin # S_PAR64 AA10 S_REQ64# AB13 S_ACK64# AA8 3.2.5 CLOCK SIGNALS Name Pin # P_CLK E21 S_CLK AB23 2-PORT PCI-X BRIDGE ADVANCE INFORMATION Type Description TS Secondary Upper 32-bit Parity: S_PAR64 carries the even parity of S_AD[63:32] and S_CBE[7:4] ...
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STRAPPING PINS AND MISCELLANEOUS SIGNALS Name Pin # S__ARB# T21 S_SEL100 V3 S_PCIXCAP R23 S_PCIXCAP_PU AA1 S_DRVR AC7 P_DRVR E2 S_CLK_STABLE W3 S_IDSEL AA22 2-PORT PCI-X BRIDGE ADVANCE INFORMATION Type Description I Internal Arbiter Enable: This pin is used ...
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Y22 BAR_EN G2 IDSEL_ROUTE AC22 OPAQUE_EN AA18 P_CFG_BUSY C6 RESERVED D1 3.2.7 JTAG BOUNDARY SCAN AND TEST SIGNALS Name Pin # TCK F21 TMS D22 TDO B23 TDI C22 TRST# C23 2-PORT PCI-X BRIDGE ADVANCE INFORMATION I PCI-X Device ...
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TEST SIGNALS Name Pin # T_DI1 Y21 T_DI2 AA4 T_MODECTL C1 T_RI W22 XCLK_OUT D3 T_RI W22 TEST_CE0 Y23 3.2.9 POWER AND GROUND SIGNALS Name Pin # P_VDDA A21 P_VSSA D16 S_VDDA AB21 S_VSSA Y16 VDD D9, D11, D13, ...
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Name Pin # VDD2 A8, A12, A22, C5, D5, D7, D17, D19, E4, E20, G4, G20, H23, M1, T1, U4, U20, W4, W20, Y5, Y7, Y17, Y19, AC2, AC12, AC16 VSS A1, A6, A10, A11, A14, A18, A23, B2, B22, ...
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BALL PIN NAME TYPE LOCATION D2 P_AD[47 VSS P D6 P_AD[51 VSS P D10 P_AD[62] TS D12 VSS P D14 P_CBE[2]# TS D16 P_VSSA P D18 P_AD[11] TS D20 VSS P D22 TMS I E1 P_AD[38] ...
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BALL PIN NAME TYPE LOCATION V1 VSS P V3 S_SEL100 I V20 S_AD[14] TS V22 S_AD[17 S_AD[44 S_CLK_STABLE I W20 VDD2 P W22 T_RI I Y1 S_AD[46 S_AD[56 VDD2 P Y7 VDD2 ...
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PCI BUS OPERATION This Chapter offers information about PCI transactions, transaction forwarding across PI7C21P100, and transaction termination. The PI7C21P100 has two 2KB buffers for read data buffering of upstream and downstream transactions. Also, PI7C21P100 has two 1KB buffers for ...
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WRITE TRANSACTIONS Write transactions are treated as posted write, delayed/split (PCI-X), or immediate write transactions. Table 4-2 shows the method of forwarding used for each type of write operation. Table 4-2 WRITE TRANSACTION FORWARDING Type of Transaction Memory Write ...
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PI7C21P100 ends the transaction on the target bus when one of the following conditions is met: All posted write data has been delivered to the target. The target returns a target disconnect or target retry (PI7C21P100 starts another transaction to ...
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PCI-X TO PCI When the originating bus is operating in the PCI-X mode and the destination bus is operating in the conventional PCI mode, PI7C21P100 uses the PCI conventional memory write command for both the PCI-X memory write and ...
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MEMORY READ TRANSACTIONS Memory data is transferred from the originating side of PI7C21P100 to the destination side using PCI memory read, memory read line, memory read multiple, PCI-X memory read DWORD, and PCI-X memory read block transactions. All memory ...
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PI7C21P100 must translate the conventional PCI memory read multiple command to the memory read block PCI-X command. Bits [21:20] offset 40h and bits [5:4] offset 40h control the mode of prefetching for memory read multiple transactions in the prefetchable range ...
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NON-PREFETCHABLE AND DWORD READS A non-prefetchable read transaction is a read transaction in which PI7C21P100 requests exactly one DWORD from the target and disconnects the initiator after delivering that one DWORD of read data. Unlike prefetchable read transactions, PI7C21P100 ...
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Primary and Secondary Data Buffering Control ...
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The register number is found in both Type 0 and Type 1 formats and gives the DWORD address of the configuration register to be accessed. The function number is also included in both Type 0 and Type 1 formats and ...
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The bus number in address field P_AD[23:16] is equal to the value in the secondary bus number register in configuration space. P_CBE[3:0 configuration read or configuration write transaction. When PI7C21P100 translates the Type 1 transaction to a Type ...
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The lowest two address bits on P_AD[1:0] are equal to 01b. The bus number falls in the range defined by the lower limit (exclusive) in the secondary bus number register and the upper limit (inclusive) in the subordinate bus number ...
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GENERAL ORDERING GUIDELINES Independent transactions on primary and secondary buses have a relationship only when those transactions cross PI7C21P100. The following general ordering guidelines govern transactions crossing PI7C21P100: Requests terminated with target retry can be accepted and completed in ...
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Pass Delayed Read Completion Delayed Write Completion 1. If the relaxed ordering bit is set in PCI-X to PCI-X mode, or the enable relaxed ordering bit in the primary and/or secondary data buffering control registers is set in any other ...
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SECONDARY BUS The secondary interface is capable of operating in either conventional PCI mode or in PCI-X mode. PI7C21P100 controls the mode and frequency for the secondary bus by utilizing a pull- up circuit connected to S_PCIXCAP. There are ...
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CLOCK STABILITY To comply with PCI and PCI-X architecture specifications, the bus clock must be stable and running at the designated frequency for at least 100us after deassertion of the bus reset. S_CLK_STABLE is used to determine and detect ...
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PRIMARY INTERFACE RESET When P_RST# is asserted, the following events occur: PI7C21P100 immediately tri-states all primary PCI interface signals. S_AD[31:0] and S_CBE[3:0] are driven LOW on the secondary interface and other control signals are tri- stated. PI7C21P100 performs a ...
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Table 7-1 DELAY TIMES FOR DE-ASSERTION OF S_RST# Conventional PCI 7 primary clock T PIRSTDLY cycles 6675 primary clock T XCAP cycles 11 secondary and 7 T SRSTDLY primary clock cycles 16 secondary clock T SIRSTDLY cycles Note: Primary and ...
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S_AD(31)). The device mask bit options (device numbers and 13) defined by PI7C21P100 allow architectures to support private device groupings that use a single or ...
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Applications that do not require access to the bridge configuration registers via the secondary bus should pull both the S_IDSEL and P_CFG_BUSY pins LOW. 7.8 SHORT TERM CACHING Short Term Caching is a means to provide ...
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CONFIGURATION REGISTERS PCI configuration defines a 64 DWORD space to define various attributes of PI7C21P100. 8.1 CONFIGURATION REGISTER SPACE MAP Table 8-1 CONFIGURATION SPACE MAP 31 – 24 Device ID Primary Status BIST Secondary Latency Timer Secondary Status Memory ...
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SIGNAL TYPE DEFINITION SIGNAL TYPE RO RW RWC 8.1.2 VENDOR ID REGISTER – OFFSET 00h BIT FUNCTION 15:0 Vendor ID 8.1.3 DEVICE ID REGISTER – OFFSET 00h BIT FUNCTION 31:16 Device ID 8.1.4 COMMAND REGISTER – OFFSET 04h BIT ...
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BIT FUNCTION 2 Bus Master Enable 1 Memory Space Enable 0 I/O Space Enable 8.1.5 PRIMARY STATUS REGISTER – OFFSET 04h BIT FUNCTION 31 Detected Parity Error 30 Signaled System Error 29 Received Master Abort 28 Received Target Abort 27 ...
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REVISION ID REGISTER – OFFSET 08h BIT FUNCTION 7:0 Revision ID 8.1.7 CLASS CODE REGISTER – OFFSET 08h BIT FUNCTION 31:24 Class Code 23:16 Sub Class Code 15:8 Programming Interface 8.1.8 CACHE LINE SIZE REGISTER – OFFSET 0Ch BIT ...
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LOWER MEMORY BASE ADDRESS REGISTER – OFFSET 10h BIT FUNCTION 31:20 Memory Base Address 19:4 Reserved 3 Prefetchable Indicator 2:1 Decoder Width 0 Decoder Type 8.1.13 UPPER MEMORY BASE ADDRESS REGISTER – OFFSET 14h BIT FUNCTION 31:0 Upper Memory ...
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I/O BASE ADDRESS REGISTER – OFFSET 1Ch BIT FUNCTION 7:4 I/O Base Address 3:2 Reserved 1:0 32-bit I/O Addressing 8.1.19 I/O LIMIT REGISTER – OFFSET 1Ch BIT FUNCTION 15:12 I/O Limit Address 11:10 Reserved 9:8 32-bit I/O Addressing 8.1.20 ...
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BIT FUNCTION 21 66MHz Capable 20:16 Reserved 8.1.21 MEMORY BASE REGISTER – OFFSET 20h BIT FUNCTION 15:4 Memory Base 3:0 Reserved 8.1.22 MEMORY LIMIT REGISTER – OFFSET 20h BIT FUNCTION 31:20 Memory Limit 19:16 Reserved 8.1.23 PREFETCHABLE MEMORY BASE REGISTER ...
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PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch BIT FUNCTION 31:0 Prefetchable Limit Upper 32-bit 8.1.27 I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h BIT FUNCTION 15:0 I/O Base Upper 16-bit 8.1.28 I/O LIMIT UPPER 16-BIT REGISTER – OFFSET ...
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BRIDGE CONTROL REGISTER – OFFSET 3Ch BIT FUNCTION 31:28 RESERVED 27 Discard Timer P_SERR# Enable 26 Master Timeout Status 25 Secondary Master Timeout Status 24 Primary Master Timeout Status 23 Fast Back-to-Back 22 Secondary Interface Reset 21 Master Abort ...
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BIT FUNCTION 16 Parity Error Response Enable 8.1.34 PRIMARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h BIT FUNCTION 15 RESERVED 14:12 Maximum Memory Read Byte Count 11 Enable Relaxed Ordering 10 Primary Special Delayed Read Mode Enable 9:8 Primary Read ...
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SECONDARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h BIT FUNCTION 31 RESERVED 30.28 Maximum Memory Read Byte Count 27 Enable Relaxed Ordering 26 Secondary Special Delayed Read Mode Enable 25:24 Secondary Read Prefetch Mode 23:22 Secondary Read Line Prefetch ...
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MISCELLANEOUS CONTROL REGISTER – OFFSET 44h BIT FUNCTION 7:3 RESERVED 2 Primary Configuration Busy 1 Data Parity Error Recovery Enable 0 Parity Error Behavior 8.1.37 EXTENDED CHIP CONTROL REGISTER 1 – OFFSET 48h BIT FUNCTION 7 RESERVED 6 Bridge ...
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BIT FUNCTION 2 Downstream Memory Read Prefetching Dynamic Control 1:0 RESERVED 8.1.38 EXTENDED CHIP CONTROL REGISTER 2 – OFFSET 48h BIT FUNCTION 11:10 Minimum Free Space in Memory Data FIFO Control (Secondary) 9:8 Minimum Free Space in Memory Data FIFO ...
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BIT FUNCTION 0 External Arbiter 8.1.40 ARBITER ENABLE REGISTER – OFFSET 54h BIT FUNCTION 7 RESERVED 6 Enable Arbiter 6 5 Enable Arbiter 5 4 Enable Arbiter 4 3 Enable Arbiter 3 2 Enable Arbiter 2 1 Enable Arbiter 1 ...
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BIT FUNCTION 2 Arbiter Priority 2 1 Arbiter Priority 1 0 Arbiter Priority 0 8.1.42 SERR# DISABLE REGISTER – OFFSET 5Ch BIT FUNCTION 7:5 RESERVED 4 PERR# on Posted Writes SERR# Disable 3 Primary Discard Timer SERR# Disable 2 Secondary ...
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PRIMARY RETRY COUNTER REGISTER – OFFSET 60h BIT FUNCTION 31 2G Retry Count Control 30:25 RESERVED 24 16M Retry Count Control 23:17 RESERVED 16 64K Retry Count Control 15:9 RESERVED 8 256 Retry Count Control 7:0 RESERVED The below ...
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DISCARD TIMER CONTROL REGISTER – OFFSET 68h BIT FUNCTION 7:4 RESERVED 3 Primary Discard Timer Short Duration 2 Secondary Discard Timer Short Duration 1 Primary Discard Timer Disable 0 Secondary Discard Timer Disable 8.1.46 RETRY AND TIMER STATUS REGISTER ...
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OPAQUE MEMORY BASE REGISTER – OFFSET 74h BIT FUNCTION 15:4 Opaque Memory Base Address 3:0 Address Select 8.1.49 OPAQUE MEMORY LIMIT REGISTER – OFFSET 74h BIT FUNCTION 31:20 Opaque Memory Limit Address 19:16 Address Select 8.1.50 OPAQUE MEMORY BASE ...
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NEXT CAPABILITY POINTER REGISTER – OFFSET 80h BIT FUNCTION 15:8 Next Capability Pointer 8.1.54 PCI-X SECONDARY STATUS REGISTER – OFFSET 80h BIT FUNCTION 31:25 RESERVED 24:22 Secondary Clock Frequency 21 Split Request Delayed 20 Split Completion Overrun 19 Unexpected ...
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BIT FUNCTION TYPE 21 Split Request Delayed RW 20 Split Completion RW Overrun 19 Unexpected Split RW Completion 18 Split Completion RW Discarded 17 133MHz Capable RO 16 64-bit Device RO 15:8 Bus Number RO 7:3 Device Number RO 2:0 ...
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SECONDARY BUS UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h BIT FUNCTION 31:16 Split Transaction Commitment Limit 15:0 Split Transaction Capability 8.1.57 PRIMARY BUS DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch BIT FUNCTION 31:16 Split Transaction Commitment Limit 15:0 Split ...
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NEXT CAPABILITIES POINTER REGISTER – OFFSET 90h BIT FUNCTION 15:8 Next Capabilities Pointer 8.1.60 POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 90h BIT FUNCTION 31:27 PME# Pin Support 26 D2 Power State Support 25 D1 Power State Support 24:22 AUX ...
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BIT FUNCTION 1:0 Power State 8.1.62 PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER – OFFSET 94h BIT FUNCTION 31:24 Data Register 23 Bus Power / Clock Control 22 B2/B3 Support for D3 HOT 21:16 RESERVED 8.1.63 SECONDARY BUS PRIVATE DEVICE MASK REGISTER ...
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BIT FUNCTION 20 Private Device Mask 4 19:18 RESERVED 17 Private Device Mask 1 16:0 RESERVED 8.1.64 MISCELLANEOUS CONTROL REGISTER 2 – OFFSET B8h BIT FUNCTION 15 Short Term Caching 14:10 RESERVED 9 Primary Prefetching Persistence Control 8 Secondary Prefetching ...
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IEEE 1149.1 COMPATIBLE JTAG CONTROLLER An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support boundary scan in PI721P100 for board-level continuity test and diagnostics. The TAP pins assigned are TCK, TDI, ...
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BOUNDARY SCAN REGISTER The boundary scan register is a required set of serial-shiftable register cells, formed by connecting boundary scan cells placed at the device’s signal pins into a shift register path. The VDD, VSS, and JTAG pins are ...
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Boundary Scan Register Number Pin Name 33 P_AD[32] 34 P_AD[33] 35 P_AD[34] 36 P_AD[35] 37 P_AD[36] 38 P_AD[37] 39 P_AD[38] 40 P_AD[39] 41 P_AD[40] 42 P_AD[41] 43 P_AD[42] 44 P_AD[43] 45 P_AD[44] 46 P_AD[45] 47 P_AD[46] 48 P_AD[47] 49 P_AD[48] ...
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Boundary Scan Register Number Pin Name 85 P_REQ64 86 P_REQ 87 P_RST 88 P_SERR 89 P_STOP 90 P_TRDY 91 S_ACK64 92 S_AD[0] 93 S_AD[1] 94 S_AD[2] 95 S_AD[3] 96 S_AD[4] 97 S_AD[5] 98 S_AD[6] 99 S_AD[7] 100 S_AD[8] 101 S_AD[9] ...
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Boundary Scan Register Number Pin Name 137 S_AD[45] 138 S_AD[46] 139 S_AD[47] 140 S_AD[48] 141 S_AD[49] 142 S_AD[50] 143 S_AD[51] 144 S_AD[52] 145 S_AD[53] 146 S_AD[54] 147 S_AD[55] 148 S_AD[56] 149 S_AD[57] 150 S_AD[58] 151 S_AD[59] 152 S_AD[60] 153 S_AD[61] ...
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Boundary Scan Register Number Pin Name 189 S_REQ[6] 190 S_RST 191 S_SEL100 192 S_SERR 193 S_STOP 194 S_TRDY 195 BAR_EN 196 RESERVED 197 XCLK_OUT 198 S_IDSEL 199 64BIT_DEV 200 IDSEL_ROUTE 201 OPAQUE_EN 202 - 203 - 204 - 205 - ...
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Boundary Scan Register Number Pin Name 241 - 242 - 243 - 244 - 245 - 246 - 247 - 248 - 249 - 250 - 251 - 252 - 253 - 254 - 255 - 256 - 257 - ...
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Boundary Scan Register Number Pin Name 293 - 294 - 295 - 296 - 297 - 298 - 299 - 300 - 301 - 302 - 303 - 304 - 305 - 306 - 307 - 308 - 309 - ...
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Boundary Scan Register Number Pin Name 345 - 346 - 347 - 348 - 349 - 350 - 351 - 352 - 353 - 354 - 355 - 356 - 357 - 358 - 359 - 360 - 361 - ...
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ELECTRICAL INFORMATION 10.1 MAXIMUM RATINGS Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions above those ...
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Table 10-1 AC TIMING SPECIFICATIONS PCI-X MODE Symbol Parameter Input setup time to CLK – bussed T su signals Input setup time to CLK – point-to- T su(ptp) point signals Input signal hold time from CLK T h CLK to ...
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... MECHANICAL INFORMATION Figure 11-1 PACKAGE DIAGRAM 31 X 31mm 304-PIN CSBGA 12 ORDERING INFORMATION PART NUMBER PI7C21P100NH PI7C21P100NH ADVANCE INFORMATION SPEED PIN – PACKAGE 133MHz 304-PINS – CSGA 133MHz Pb-free & Green, 304-PINS - CSBGA Page PI7C21P100 2-PORT PCI-X BRIDGE TEMPERATURE 0°C TO 85°C 0° ...
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NOTES: Page PI7C21P100 2-PORT PCI-X BRIDGE ADVANCE INFORMATION June 10, 2005 Revision 1.06 ...