PI7C21P100NH PERICOM [Pericom Semiconductor Corporation], PI7C21P100NH Datasheet - Page 50

• Manufacturer Part Number: PI7C21P100NH
• Description: 2-PORT PCI-X BRIDGE
• Manufacturer: PERICOM [Pericom Semiconductor Corporation]

8.1.34
PRIMARY DATA BUFFERING CONTROL REGISTER – OFFSET 40h
BIT
16
BIT
15
14:12
11
10
9:8
7:6
5:4
3:0
FUNCTION
Parity Error Response
Enable
FUNCTION
RESERVED
Maximum Memory
Read Byte Count
Enable Relaxed
Ordering
Primary Special
Delayed Read Mode
Enable
Primary Read Prefetch
Mode
Primary Read Line
Prefetch Mode
Primary Read Multiple
Prefetch Mode
RESERVED
TYPE
TYPE
RW
RO
RW
RW
RW
RW
RW
RW
RO
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DESCRIPTION
Parity Error Response Enable
0: Ignore address and data parity errors on the secondary interface.
1: Enable parity error detection on the secondary interface.
DESCRIPTION
Reserved. Returns 0h when read.
Maximum Memory Read Byte Count
000: 512 bytes (default)
001: 128 bytes
010: 256 bytes
011: 512 bytes
100: 1024 bytes
101: 2048 bytes
110: 4096 bytes
111: 512 bytes
Maximum byte count is used by PI7C21P100 when generating read
requests on the secondary interface in response to a memory read
operation initiated on the primary interface which is in PCI mode and
bits[9:8], bits[7:6], or bits[5:4] are set to full prefetch.
Reset to 000
Relaxed Ordering Enable
0: Relaxed ordering is disabled in conventional PCI mode.
1: At the primary interface, read completions that occur after the first
read completion are allowed to bypass posted writes and complete
with a higher priority in conventional PCI mode.
In PCI-X mode, the relaxed ordering bit in the attribute field will
take precedence. Reset to 0
Primary Special Delayed Read Mode Enable
0: Retry any primary master which repeats its transaction with
command code changes.
1: Allows any primary master to change memory command code
(MR, MRL, MRM) after it has received a retry. PI7C21P100 will
complete the memory read transaction and return data back to the
primary bus master if the address and byte enables are the same.
This bit is ignored in PCI-X mode. Reset to 0
Primary Read Prefetch Mode
00: One cache line prefetch if memory read address is in the
prefetchable range at the primary interface
01: Reserved
10: Full prefetch if memory read address is in the prefetchable range
at the primary interface.
11: Disconnect on the first DWORD.
These bits are ignored in PCI-X mode. Reset to 00
Primary Read Line Prefetch Mode
00: One cache line prefetch if memory read line address is in
prefetchable range at the primary interace
01: Reserved
10: Full prefetch if memory read multiple address is in prefetchable
range at the primary interface
11: Reserved.
These bits are ignored if the primary interface is in PCI-X mode.
Primary Read Multiple Prefetch Mode
00: One cache line prefetch if memory read multiple address is in
prefetchable range at the primary interface.
01: Reserved.
10: Full prefetch if memory read multiple address is in prefetchable
range at the primary interface.
11: Reserved.
These bits are ignored if the primary interface is in PCI-X mode.
Reset to 10.
Reserved. Returns 0000 when read.
ADVANCE INFORMATION
June 10, 2005 Revision 1.06
2-PORT PCI-X BRIDGE
PI7C21P100