ICS85322AMI ICST [Integrated Circuit Systems], ICS85322AMI Datasheet - Page 6

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ICS85322AMI

Manufacturer Part Number
ICS85322AMI
Description
DUAL LVCMOS / LVTTL-TO-DIFFERENTIAL 2.5V / 3.3V LVPECL TRANSLATOR
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
T
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
85322AMI
RTT =
ERMINATION FOR
F
(V
FOUT
IGURE
OH
+ V
OL
Integrated
Circuit
Systems, Inc.
1A. LVPECL O
/ V
1
CC
3.3V LVPECL O
– 2) – 2
Z
Z
o
o
= 50
= 50
Z
o
50
UTPUT
A
T
RTT
ERMINATION
50
UTPUTS
PPLICATION
www.icst.com/products/hiperclocks.html
V
CC
FIN
- 2V
6
I
50 transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 1A and 1B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
NFORMATION
D
UAL
FOUT
F
LVCMOS / LVTTL-
IGURE
2.5V / 3.3V LVPECL T
1B. LVPECL O
Z
Z
o
o
= 50
= 50
125
84
UTPUT
3.3V
TO
ICS85322I
125
84
T
-D
ERMINATION
REV. B OCTOBER 7, 2003
IFFERENTIAL
RANSLATOR
FIN

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