MC146805E2CFN INNOVASIC [InnovASIC, Inc], MC146805E2CFN Datasheet - Page 22

• Manufacturer Part Number: MC146805E2CFN
• Description: Microprocessor Unit
• Manufacturer: INNOVASIC [InnovASIC, Inc]

Low
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IA6805E2
Microprocessor Unit
Opcode Map Summary:
Abbreviations for Address
Modes:
INH
A
X
IMM
DIR
EXT
Copyright
Hi
innovASIC
A
D
0
1
2
3
4
5
6
7
8
9
B
C
E
F
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
Bit Manipulation
BRSET0
BRCLR0
BRSET1
BRCLR1
BRSET2
BRCLR2
BRSET3
BRCLR3
BRSET4
BRCLR4
BRSET5
BRCLR5
BRSET6
BRCLR6
BRSET7
BRCLR7
BTB
0000
0
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
BTB 2
The following table is an opcode map for the instructions used on the MPU. The legend
following the table shows how to use the table.
Inherent
Accumulator
Index Register
Immediate
Direct
Extended
2002
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
The End of Obsolescence
BSET0
BCLR0
BSET1
BCLR1
BSET2
BCLR2
BSET3
BCLR3
BSET4
BCLR4
BSET5
BCLR5
BSET6
BCLR6
BSET7
BCLR7
0001
BSC
1
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
BSC 2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Branch
BHCC
BHCS
BMC
REL
0010
BRA
BRN
BCC
BNE
BEQ
BMS
BHI
BLS
BCS
BPL
BMI
BIH
BIL
2
REL 2
REL
REL
REL 2
REL 2
REL
REL 2
REL 2
REL 2
REL 2
REL 2
REL
REL 2
REL 2
REL
REL 2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
NEG
COM
0011
ROR
ROL
DEC
DIR
LSR
ASR
LSL
INC
TST
CLR
3
DIR 1
DIR 1
DIR 1
DIR 1
DIR 1
DIR 1
DIR 1
DIR 1
DIR 1
DIR 1
DIR 1
5
5
5
5
5
5
5
5
5
4
5
NEGA
COMA
RORA
ROLA
DECA
Read-Modify-Write
LSRA
ASRA
INCA
TSTA
CLRA
LSLA
INH
0100
4
INH 1
INH 1
INH 1
INH 1
INH 1
INH 1
INH 1
INH 1
INH 1
INH 1
INH 1
3
3
3
3
3
3
3
3
3
3
3
REL
BSC
BTB
IX
IX1
IX2
Legend:
NEGX
COMX
RORX
ROLX
DECX
LSRX
ASRX
LSLX
INCX
TSTX
CLRX
INH
0101
5
INH 2
INH 2
INH 2
INH 2
INH 2
INH 2
INH 2
INH 2
INH 2
INH 2
INH 2
3
3
3
3
3
3
3
3
3
3
3
Relative
Bit set/clear
Bit test and branch
Indexed, no offset
Indexed, 1 byte offset
Indexed, 2 byte offset
ENG21108140100
COM
NEG
ROR
DEC
0110
ASR
ROL
INC
CLR
IX1
LSR
LSL
TST
6
Page 22 of 31
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
6
6
6
6
6
6
6
6
6
6
6
NEG
COM
ROR
ROL
DEC
0111
ASR
INC
TST
CLR
LSR
LSL
IX
7
IX 1
IX 1
IX
IX
IX
IX
IX
IX
IX
IX
IX 1
5
5
5
5
5
5
5
5
5
4
5
1
1
STOP
WAIT
INH
1000
RTS
SWI
RTI
8
Control
INH
INH
INH
INH
INH 1
10
9
6
2
2
1
1
1
1
1
1
1
NOP
INH
TAX
TXA
1001
CLC
SEC
RSP
CLI
SEI
9
INH
INH 2
INH 2
INH 2
INH 2
INH
INH 2
INH
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
AND
ADC
ADD
As of Production Version 00
IMM
1010
CMP
CPX
LDA
EOR
ORA
LDX
SUB
SBC
BIT
BSR
A
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
IMM 2
2
2
2
2
2
2
2
2
2
2
2
6
2
2
2
2
AND
EOR
ADC
ORA
ADD
1011
SUB
CMP
CPX
LDA
LDX
DIR
SBC
BIT
STA
JMP
STX
JSR
B
# of Cycles
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
DIR 3
Mnemonic
Register/Memory
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
Bytes
CMP
AND
LDA
EOR
ADC
ORA
ADD
LDX
EXT
1100
SUB
SBC
CPX
STA
STX
BIT
JMP
JSR
C
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
EXT 3
Data Sheet
4
4
4
4
4
4
4
5
4
4
4
4
3
6
4
5
1
AND
ADD
CMP
LDA
EOR
ADC
ORA
LDX
1101
SUB
SBC
CPX
STA
JMP
STX
IX2
BIT
1111
JSR
SUB
D
www.innovasic.com
Customer Support:
F
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
IX2 2
1-888-824-4184
5
5
5
5
5
5
5
6
5
5
5
5
4
7
5
6
IX
3
AND
ADD
CMP
LDA
EOR
ADC
ORA
LDX
1110
SUB
SBC
CPX
STA
JMP
STX
IX1
BIT
JSR
E
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
IX1 1
4
4
4
4
4
4
4
5
4
4
4
4
3
6
4
5
0000
0
AND
ADD
CMP
CPX
LDA
EOR
ADC
ORA
LDX
1111
SUB
SBC
STA
JMP
STX
BIT
JSR
IX
F
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
IX
3
3
3
3
3
3
3
4
3
3
3
3
2
5
3
4
Opcode in Hexadecimal
A 1010
B 1011
C 1100
D 1101
E 1110
F 1111
Opcode in Binary
Address Mode
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
Low
Hi