AD7357_08 AD [Analog Devices], AD7357_08 Datasheet - Page 15

• Manufacturer Part Number: AD7357_08
• Description: Differential Input, Dual, Simultaneous Sampling, 4.2 MSPS, 14-Bit, SAR ADC
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
MODES OF OPERATION
The mode of operation of the AD7357 is selected by controlling
the logic state of the CS signal during a conversion. There are
three possible modes of operation: normal mode, partial power-
down mode, and full power-down mode. After a conversion has
been initiated, the point at which CS is pulled high determines
which power-down mode, if any, the device enters. Similarly, if
already in a power-down mode, CS can control whether the
device returns to normal operation or remains in a power-down
mode. These modes of operation are designed to provide
flexible power management options. These options can be
chosen to optimize the power dissipation/throughput rate ratio
for the differing application requirements.
NORMAL MODE
Normal mode is intended for applications needing the fastest
throughput rates. The user does not have to worry about any
power-up times because the AD7357 remains fully powered at
all times. Figure 24 shows the general diagram of the operation
of the AD7357 in this mode.
The conversion is initiated on the falling edge of CS , as
described in the Serial Interface Error! Reference source not
found. section. To ensure that the part remains fully powered
up at all times, CS must remain low until at least 10 SCLK
falling edges have elapsed after the falling edge of CS . If CS is
brought high any time after the 10
before the 16
but the conversion is terminated and SDATA
back into three-state. 16 serial clock cycles are required to
complete the conversion and access the conversion result for the
AD7357. The SDATA lines do not return to three-state after 16
SCLK cycles have elapsed, but instead do so when CS is brought
high again. If CS is left low for another 2 SCLK cycles, two
trailing zeros are clocked out after the data. If CS is left low for a
further 16 SCLK cycles, the result for the other ADC on board
is also accessed on the same SDATA line as shown in Figure 31
(see the Serial Interface section).
Once 32 SCLK cycles have elapsed, the SDATA line returns to
three-state on the 32
prior to this, the SDATA line returns to three-state at that point.
Thus, CS may idle low after 32 SCLK cycles until it is brought
high again sometime prior to the next conversion if so desired,
because the bus still returns to three-state upon completion of
the dual result read.
D
D
SCLK
OUT
OUT
CS
A
B
th
SCLK falling edge, the part remains powered up,
1
Figure 24. Normal Mode Operation
LEADING ZEROS + CONVERSION RESULT
nd
SCLK falling edge. If CS is brought high
th
SCLK falling edge but
10
A
and SDATA
14
B
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go
Once a data transfer is complete and SDATA
returned to three-state, another conversion can be initiated after
the quiet time, t
(assuming the required acquisition time has been allowed).
PARTIAL POWER-DOWN MODE
This mode is intended for use in applications where slower
throughput rates are required. Either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of several conversions. When the AD7357 is in partial
power-down, all analog circuitry is powered down except for
the on-chip reference and reference buffers.
To enter partial power-down mode, the conversion process
must be interrupted by bringing CS high anywhere after the
second falling edge of SCLK and before the 10
SCLK, as shown in Figure 25. Once CS has been brought high
in this window of SCLKs, the part enters partial power-down
mode, the conversion that was initiated by the falling edge of CS
is terminated, and SDATA
state. If CS is brought high before the second SCLK falling edge,
the part remains in normal mode and does not power down.
This avoids accidental power-down due to glitches on the CS
line.
To exit this mode of operation and power up the AD7357 again,
perform a dummy conversion. On the falling of CS , the device
begins to power up, and continues to power up as long as CS is
held low until after the falling edge of the 10
is fully powered up after approximately 200 ns has elapsed (or
one full conversion), and valid data results from the next
conversion, as shown in Figure 26. If CS is brought high before
the second falling edge of SCLK, the AD7357 again goes into
partial power-down mode. This avoids accidental power-up due
to glitches on the CS line. Although the device may begin to
power up on the falling edge of CS , it powers down again on the
rising edge of CS . If the AD7357 is already in partial power-
down mode and CS is brought high between the second and
10
mode.
D
D
SCLK
th
OUT
OUT
falling edges of SCLK, the device enters full power-down
CS
A
B
Figure 25. Entering Partial Power-Down Mode
QUIET
1
2
, has elapsed by bringing CS low again
A
and SDATA
B
10
go back into three-
THREE-STATE
th
A
SCLK. The device
and SDATA
th
falling edge of
14
AD7357
B
have