VSP2260Y/2KC BURR-BROWN [Burr-Brown Corporation], VSP2260Y/2KC Datasheet - Page 9

• Manufacturer Part Number: VSP2260Y/2KC
• Description: CCD SIGNAL PROCESSOR for DIGITAL CAMERAS
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

output data comes out on the rising edge of ADCCK with a
delay of nine clock cycles (data latency is nine).
If the input voltage is higher than the supply rail by 0.3V, or
lower than the ground rail by 0.3V, the protection diodes
will be turned on to prevent the input voltage from going any
further. Such a high swing signal may cause device damage
to the VSP2260 and should be avoided.
STAND-BY MODE
For the purpose of saving power, the VSP2260 can be set to
Stand-by mode (or Power-Down mode) through the serial
interface when the VSP2260 is not in use. Refer to the
“Serial Interface” section for more detail. In this mode, all
the function blocks are disabled and the digital outputs will
go to all ZEROs, causing the current consumption to drop to
1mA. Since all the bypass capacitors will discharge during
this mode, a substantial time (usually of the order of 200ms
to 300ms) is required to power up from Stand-by mode.
VOLTAGE REFERENCE
All the reference voltages and bias currents needed in the
VSP2260 are generated by its internal bandgap circuitry.
The CDS and the ADC use mainly three reference voltages:
REFP (Positive Reference, pin 38), REFN (Negative Refer-
ence, pin 39) and CM (Common-Mode Voltage, pin 37).
REFP, REFN and CM should be heavily decoupled with
appropriate capacitors (e.g., 0.1 F ceramic capacitor). Do
not use these voltages elsewhere in the system as they affect
the stability of the reference level, and cause ADC perfor-
mance degradation. Note that these are analog output pins
and do not apply external voltage.
BYPP2 (pin 29), BYP (pin 31), and BYPM (pin 32) are also
reference voltages to be used in the analog circuit. BYP
should be connected to ground with a 0.1 F ceramic capaci-
VSP2260
SBMS010
tor. Since the capacitor value for BYPP2 and BYPM affects
the step response, we consider 400pF to 9000pF to be a
reasonable value. However, as it depends on the application
environment, we recommend making careful adjustments
using trial-and-error.
BYPP2, BYP and BYPM should all be heavily decoupled
with appropriate capacitors, and not used elsewhere in the
system. They affect the stability of the reference levels, and
cause performance degradation. Note that these are analog
output pins and do not apply external voltage.
SERIAL INTERFACE
The serial interface has a 2-byte shift register and various
parallel registers to control all the digitally programmable
features of the VSP2260. Writing to these registers is con-
trolled by four signals (SLOAD, SCLK, SDATA, and RE-
SET). To enable the shift register, SLOAD must be pulled
LOW. SDATA is the serial data input and the SCLK is the
shift clock. The data at SDATA is taken into the shift
register at the rising edge of SCLK; the data length should
be two bytes. After the 2-byte shift operation, the data in the
shift register is transferred to the parallel latch at the rising
edge of SLOAD. In addition to the parallel latch, there are
several registers dedicated to the specific features of the
device and are synchronized with ADCCK. It takes five or
six clock cycles for the data in the parallel latch to be written
to those registers. Therefore, to complete the data updates, it
requires five or six clock cycles after parallel latching by the
rising edge of SLOAD.
See Table II for the serial interface data format. TEST is the
flag for the test mode (Texas Instruments proprietary only),
A0 to A2 is the address for the various registers, and D0 to
D11 is the data (or operand) field.
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