AD5062BRJ-1 AD [Analog Devices], AD5062BRJ-1 Datasheet - Page 12

• Manufacturer Part Number: AD5062BRJ-1
• Description: Full Accurate 16 Bit Vout nanoDac, 2.7V- 5.5V, in a Sot 23
• Manufacturer: AD [Analog Devices]

AD5062/AD5063
GENERAL DESCRIPTION
The AD5062/AD5063 are single 16-bit, serial input, voltage
output DACs. It operates from supply voltages of 2.7-5.5 V. Data
is written to the AD5062/63 in a 24-bit word format, via a 3-
wire serial interface
The AD5062/AD5063 incorporates a power-on reset circuit,
which ensures that the DAC output powers up to 0 V or mid-
scale. The device also has a software power-down mode pin,
which reduces the typical current consumption to XX.
DAC Architecture
The DAC architecture of the AD5062/AD5063 consists of two
matched DAC sections. A simplifed circuit diagram is shown in
Figure X The four MSBs of the 16-bit data word are decoded to
drive 15 switches, E1 to E15. Each of these switches connects
one of 15 matched resistors to either AGND or VREF. The
remaining 12 bits of thedata word drive switches S0 to S11 of a
12-bit voltage modeR-2R ladder network.
Reference Buffer
The AD5062/AD5063 operates with an external reference.
The reference input (REFIN) has an input range of up to
4.096 V. This input voltage is then used to provide a
Figure X. DAC Ladder Structure
Figure 22. Input Register Contents
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SERIAL INTERFACE
The AD5062/AD5063 have a three-wire serial
interface (SYNC, SCLK and DIN), which is
compatible with SPI, QSPI and MICROWIRE interface
standards as well as most DSPs. See Figure 1 for a timing
diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low.
Data from the DIN line is clocked into the 24-bit shift register
on the falling edge of SCLK. The serial clock frequency can be
as high as 30 MHz, making these parts compatible with high
speed DSPs. On the 24th falling clock edge, the last data bit is
clocked in and the programmed function is executed (i.e., a
change in DAC register contents and/or a change in the mode
of operation). At this stage, the SYNC line may be kept low or
be brought high. In either case, it must be brought high for a
minimum of 33 ns before the next write sequence so that a
falling edge of SYNC can initiate the next write sequence. Since
the SYNC buffer draws more current when V IN = 1.8 V than it
does when V IN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation of the part. As
is mentioned above, however, it must be brought high again
just before the next write sequence.
Input Shift Register
The input shift register is 24 bits wide (see Figure 22). Bit D22
is the Reset Reg bit. When this is enabled the data will be loaded
into the Reset Register. This will remain the reset code until the
part powers down. D21, D20 are control bits that control
which mode of operation the part is in (normal mode or any
one of three power-down modes). There is a more complete
description of the various modes in the Power-Down
Modes section. The next twenty bits are the data bits. These are
transferred to the DAC register on the 24th falling edge of SCLK.
buffered reference for the DAC core
Preliminary Technical Data