DSP56001FE33 MOTOROLA [Motorola, Inc], DSP56001FE33 Datasheet

DSP56001FE33

Manufacturer Part Number

DSP56001FE33

Description

24-Bit General Purpose Digital Signal Processor

Manufacturer

MOTOROLA [Motorola, Inc]

Datasheet

1.DSP56001FE33.pdf (64 pages)

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24-Bit General Purpose

Digital Signal Processor

The DSP56001 is a member of Motorola’s family of

HCMOS, low-power, general purpose Digital Signal

Processors. The DSP56001 features 512 words of full

speed, on-chip program RAM (PRAM) memory, two

256 word data RAMs, two preprogrammed data

ROMs, and special on-chip bootstrap hardware to per-

mit convenient loading of user programs into the pro-

gram RAM. It is an off-the-shelf part since the program

memory is user programmable. The core of the processor consists of three execution units operating in parallel — the data ALU,

the address generation unit, and the program controller. The DSP56001 has MCU-style on-chip peripherals, program and data

memory, as well as a memory expansion port. The MPU-style programming model and instruction set make writing efficient, com-

pact code, straightforward.

The high throughput of the DSP56001 makes it well-suited for communication, high-speed control, numeric processing, computer

and audio applications. The key features which facilitate this throughput are:

This document contains information on a new product. Specifications and information herein are subject to change without notice.

MOTOROLA INC., 1992

•

TECHNICAL DATA

SEMICONDUCTOR

MOTOROLA

Compatibility

Speed

Precision

Parallelism

Integration

Invisible Pipeline

Instruction Set

DSP56000/DSP56001

Low Power

At 16.5 million instructions per second (MIPS) with a 33 MHz clock, the DSP56001 can execute

a 1024 point complex Fast Fourier Transform in1.98 milliseconds (66,240 clock cycles).

The data paths are 24 bits wide thereby providing 144 dB of dynamic range; intermediate results

held in the 56-bit accumulators can range over 336 dB.

The data ALU, address arithmetic units, and program controller operate in parallel so that an in-

struction prefetch, a 24x24-bit multiplication, a 56-bit addition, two data moves, and two address

pointer updates using one of three types of arithmetic (linear, modulo, or reverse carry) can be

executed in a single instruction cycle. This parallelism allows a four coefficient Infinite Impulse Re-

sponse (IIR) filter section to be executed in only four cycles, the theoretical minimum for a single

multiplier architecture.

In addition to the three independent execution units, the DSP56001 has six on-chip memories,

three on-chip MCU style peripherals (Serial Communication Interface, Synchronous Serial Inter-

face, and Host Interface), a clock generator and seven buses (three address and four data), mak-

ing the overall system functionally complete and powerful, but also very low cost, low power, and

compact.

The three-stage instruction pipeline is essentially invisible to the programmer thus allowing

straightforward program development in either assembly language or a high-level language such

as ANSI C.

The 62 instruction mnemonics are MCU-like making the transition from programming micropro-

cessors to programming the DSP56001 digital signal processor as easy as possible. The orthog-

onal syntax supports control of the parallel execution units. This syntax provides 12,808,830 dif-

ferent instruction variations using the 62 instruction mnemonics. The no-overhead DO instruction

and the REPEAT (REP) instruction make writing straight-line code obsolete.

The DSP56001 is identical to the DSP56000 except that it has 512x24-bits of on-chip program

RAM instead of 3.75K of program ROM; a 32x24-bit bootstrap ROM for loading the program RAM

from either a byte-wide memory mapped ROM or via the Host Interface; and the on-chip X and Y

Data ROMs have been preprogrammed as positive Mu- and A-Law to linear expansion tables and

a full, four quadrant sine wave table, respectively.

As a CMOS part, the DSP56001 is inherently very low power; however, three other features can

reduce power consumption to an exceptionally low level.

— The WAIT instruction shuts off the clock in the central processor portion of the DSP56001.

— The STOP instruction halts the internal oscillator.

— Power increases linearly (approximately) with frequency; thus, reducing the clock frequency

reduces power consumption.

Ceramic Quad Flat Pack (CQFP)

Available in a 132 pin, small footprint,

surface mount package.

Plastic Quad Flat Pack (PQFP)

Available in a 132 pin, small footprint,

surface mount package.

Pin Grid Array (PGA)

Available in an 88 pin ceramic

through-hole package.

DSP56001

Order this document

by DSP56001/D

May 4, 1998

Rev. 3

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