ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet

ADSP-BF522

Manufacturer Part Number

ADSP-BF522

Description

Blackfin Embedded Processor

Manufacturer

AD [Analog Devices]

Datasheet

1.ADSP-BF522.pdf (80 pages)

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Preliminary Technical Data

FEATURES

Up to 600 MHz high-performance Blackfin processor

Accepts a wide range of supply voltages for internal and I/O

Programmable on-chip voltage regulator

289-ball (12 mm x 12 mm) and 208-ball (17 mm x 17 mm)

MEMORY

132K bytes of on-chip memory:

External memory controller with glueless support for SDRAM

Flexible booting options from external flash, SPI, and TWI

Code Security with Lockbox

Memory management unit providing memory protection

Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.

Rev. PrG

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

RISC-like register and instruction model for ease of

Advanced debug, trace, and performance monitoring

operations. See

ADSP-BF523/525/527 on Page 29

tions for ADSP-BF522/524/526 on Page 27

(ADSP-BF523/525/527 processors only)

CSP_BGA packages

(See

and asynchronous 8-bit and 16-bit memories

memory or from host devices including SPI, TWI, and UART

One-Time-Programmable (OTP) Memory

40-bit shifter

programming and compiler-friendly support

Table 1 on Page 3

USB

*REGULATOR AVAILABLE ON ADSP-BF523/525/527 PROCESSORS ONLY

Operating Conditions for

VOLTAGE REGULATOR*

L1 INSTRUCTION

EAB

MEMORY

for L1 and L3 memory size details)

Secure Technology

FLASH, SDRAM CONTROL

EXTERNAL PORT

and

MEMORY

L1 DATA

Operating Condi-

JTAG TEST AND EMULATION

WATCHDOG TIMER

Figure 1. Processor Block Diagram

DCB

CONTROLLER

INTERRUPT

DMA

DEB

PERIPHERAL

ACCESS BUS

ADSP-BF522/523/524/525/526/527

ACCESS

BOOT

DMA

ROM

BUS

Blackfin

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

PERIPHERALS

USB 2.0 high speed on-the-go (OTG) with Integrated PHY

IEEE 802.3-compliant 10/100 Ethernet MAC

Parallel peripheral interface (PPI), supporting ITU-R 656

Host DMA port (HOSTDP)

Two dual-channel, full-duplex synchronous serial ports

12 peripheral DMAs, 2 mastered by the Ethernet MAC

Two memory-to-memory DMAs with external request lines

Event handler with 54 interrupt inputs

Serial peripheral interface (SPI) compatible port

Two UARTs with IrDA

Two-wire interface (TWI) controller

Eight 32-bit timers/counters with PWM support

32-bit up/down counter with rotary support

Real-time clock (RTC) and watchdog timer

32-bit core timer

48 general-purpose I/Os (GPIOs), with programmable

NAND flash controller (NFC)

Debug/JTAG interface

On-chip PLL capable of 0.5 to 64 frequency multiplication

video data formats

(SPORTs), supporting eight stereo I

hysteresis

OTP MEMORY

HOST DMA

COUNTER

TIMER7-1

SPORT0

SPORT1

TIMER0

UART1

UART0

EMAC

RTC

NFC

TWI

PPI

SPI

Embedded Processor

support

S channels

www.analog.com

PORT G

PORT F

PORT H

PORT J

GPIO

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