ADSP-BF531WBBCZ-4A AD [Analog Devices], ADSP-BF531WBBCZ-4A Datasheet - Page 29

• Manufacturer Part Number: ADSP-BF531WBBCZ-4A
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Parallel Peripheral Interface Timing
Table 20
interface operations.
Table 20. Parallel Peripheral Interface Timing
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics—GP Output and Frame Capture Modes
t
t
t
t
PPI_CLK frequency cannot exceed f
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
PPI_FS1
PPI_FS2
PPI_DATA
and
POLS = 1
POLS = 0
POLS = 1
POLS = 0
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK Edge
(Nonsampling Edge for Rx, Sampling Edge for Tx)
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
Figure 15 on Page 29
1
SCLK
/2
describe parallel peripheral
Figure 15. PPI GP Rx Mode with Internal Frame Sync Timing
t
HOFSPE
FRAME
SYNC IS
DRIVEN
OUT
Rev. D | Page 29 of 60 | August 2006
t
DFSPE
t
SDRPE
DATA0
IS
SAMPLED
t
HDRPE
ADSP-BF531/ADSP-BF532
V
Min
6.0
15.0
6.0
1.0
3.5
1.5
1.7
1.8
DDEXT
= 1.8 V V
Max
8.0
9.0
Min
6.0
15.0
4.0
1.0
3.5
1.5
1.7
1.8
DDEXT
= 2.5 V/3.3 V
Max
8.0
9.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns