ADSP21MOD980N AD [Analog Devices], ADSP21MOD980N Datasheet - Page 5

• Manufacturer Part Number: ADSP21MOD980N
• Description: MultiPort Internet Gateway Processor
• Manufacturer: AD [Analog Devices]

All eight modem processors have identical functions and
have equal status. Each of the modem processors is con-
nected to a common IDMA bus and each modem processor
is configured to operate in the same mode (see the slave
mode and the memory mode descriptions in
Architecture” on page
be the only mode of operation in the ADSP-21mod980N
modem pool.
SERIAL PORTS
The ADSP-21mod980N has a multichannel serial port
(SPORT) connected to each internal digital modem pro-
cessor for serial communications.
The following is a brief list of ADSP-21mod980N SPORT
features. For additional information on the internal Serial
Ports, refer to the ADSP-2100 Family User’s Manual. Each
SPORT:
•
•
•
•
•
•
A multichannel interface selectively receives and transmits a
24 or 32 word, time-division multiplexed, serial bitstream.
PIN DESCRIPTIONS
The ADSP-21mod980N is available in a 352-lead PBGA
package. In order to maintain maximum functionality and
reduce package size and pin count, some serial port, pro-
grammable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are config-
ured during RESET only, while serial port pins are software
configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins.
Table on page 6
cases where pin functionality is reconfigurable, the default
state is shown in plain text; alternate functionality is shown
in italics.
REV. PrB 6/2001
is bidirectional and has a separate, double-buffered
transmit and receive section.
can use an external serial clock or generate its own
serial clock internally.
has independent framing for the receive and transmit
sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally
generated. Frame sync signals are active high or
inverted, with either of two pulse widths and timings.
supports serial data word lengths from 3 to 16 bits and
provides optional A-law and µ-law companding accord-
ing to CCITT recommendation G.711.
receive and transmit sections can generate unique
interrupts on completing a data word transfer.
can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.
lists the pin names and their functions. In
10). The slave mode is considered to
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
“Memory
ADSP-21mod980N
5