SAA7715 PHILIPS [NXP Semiconductors], SAA7715 Datasheet - Page 9

• Manufacturer Part Number: SAA7715
• Description: Digital Signal Processor
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
8
8.1
An on-chip PLL generates the clock for the DSP. The DSP runs at a selectable frequency of maximum 70 MHz. The clock
is generated with the PLL that uses the CLK_IN of the chip to generate the DSP clock. Table 2 gives the division factors
and the values of the DSP_TURBO and the DIV_CLK_IN bits that need to be set via I
Table 2 PLL division factor per clock input.
The above table does NOT imply that the clock input is restricted to the values given in this table. The clock input is
restricted to be within the range of 8.192 to 12.228 MHz. For higher clock frequencies pin DIV_CLK_IN should be set to
logic 1 performing a divide by 2 of the CLK_IN signal and thereby doubling the CLK_IN frequency range that is allowed
(16.384 to 24.576 MHz).
8.2
A second on-chip PLL generates a selectable multiple of the sample rate frequency supplied on the word select
pin IIS_WS (= IIS_WS1). The clock generated by this so called WS_PLL is available for the user at pin SYSCLK.
Tables 3 and 4 show the I
shown in Table 10.
Table 3 Word select input range selection
Table 4 Selection of n
2001 May 07
8.192 (32 kHz
9.728 (38 kHz
11.2896 (44.1 kHz
12.288 (48 kHz
16.384 (32 kHz
18.432 (32 kHz
19.456 (38 kHz
24.576 (96 kHz
Digital Signal Processor
CLOCK INPUT (MHz)
FUNCTIONAL DESCRIPTION
sel2
PLL division factors for different clock inputs
The word select PLL
1
0
0
0
0
SAMPLE RATE OF f
256)
256)
256)
512)
576)
512)
256)
sel1
256)
0
1
1
0
0
32 to 50
50 to 96
2
f
s
C-bus settings needed to generate the n
clock at SYSCLK output
pll_div[4:0]
0BH
10H
09H
03H
00H
10H
09H
00H
s
sel0
(kHz)
0
1
0
1
0
SYSCLK (n
272
227
198
181
272
244
227
181
N
9
512
384
256
192
128
DSP_TURBO
IIS_WS1)
f
s
clock. The memory map of the I
1
1
1
1
1
1
1
1
sel_loop_div[1:0]
50% for 32 to 50 kHz input; 66%
for 50 to 96 kHz input
50%
50%
50%
50%
2
DIV_CLK_IN
C-bus (see Table 10).
01
00
0
0
0
0
1
1
1
1
DUTY FACTOR
Preliminary specification
SAA7715H
DSP_CLOCK
2
C-bus bits is
69.632
69.008
69.854
69.504
69.632
68.544
69.008
69.504
(MHz)