Z89391 ZILOG [Zilog, Inc.], Z89391 Datasheet
Z89391
Related parts for Z89391
Z89391 Summary of contents
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... Lines (Max) Device 512 24 Z89321 512 16 Z89371 512 24 Z89391 Note: *General-Purpose On-Board Peripherals Dual 8/16-Bit CODEC Interface Capable Mbps m -Law Compression Option (Decompression is Performed in Software) 16-Bit I/O Bus (Tri-Stated) Three I/O Address Pins (Latched Outputs) Wait-State Generator Three Vectored Interrupts 13-Bit General-Purpose Timer ...
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Z89321/371/391 16-Bit Digital Signal Processors The Z893XX DSPs are optimized to accommodate ad- vanced signal processing algorithms. The 24 MIPS (maxi- mum) operating performance and efficient architecture provides real-time instruction execution. Compression, fil- tering, frequency detection, audio, voice detection/synthe- sis, ...
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Zilog PIN DESCRIPTION Figure 2. Z89321/371 40-Pin DIP Pin Assignments Table 1. Z89321/371 40-Pin DIP Pin IdentiÞcation No. Symbol Function 1-3 EXT12- External Data EXT14 Bus 4 V Ground SS 5 EXT15 External Data Bus 6-7 EXT3-EXT4 External Data Bus ...
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Z89321/371/391 16-Bit Digital Signal Processors PIN DESCRIPTION (Continued) EXT0 EXT1 EXT2 RXD EXT12 EXT13 EXT14 EXT15 Figure 3. Z89321/371 44-Pin PLCC Pin Assignments VSS VSS PLCC 44 -Pin VSS ...
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Zilog Table 2. Z89321/371 44-Pin PLCC Pin IdentiÞcation No. Symbol 1 HALT 2 FS0 3 /INT0 4-5 O0-UO1 6 FS1 8-10 EXT0-EXT2 RXD 13-15 EXT12-EXT14 EXT15 18-19 EXT3-EXT4 20 ...
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Z89321/371/391 16-Bit Digital Signal Processors PIN DESCRIPTION (Continued) EXT0 EXT1 EXT2 RXD EXT12 EXT13 EXT14 EXT15 Figure 4. Z89321/371 44-Pin QFP Pin Assignments 6 33 VSS 34 VSS Z89321/371 QFP VSS ...
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Zilog Table 3. Z89321/371 44-Pin QFP Pin IdentiÞcation No. Symbol 1-2 EXT3-EXT4 4-6 EXT5-EXT7 7 TXD 8-9 EXT8-EXT9 11-12 EXT10-EXT1 13 /INT2 14 /INT1 15 UI1 16 UI0 17 SCLK ...
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... EXT5 PA10 EXT6 PA11 EXT7 TXD PA12 EXT8 PA13 EXT9 VSS PA14 EXT10 PA15 VDD 32 33 Figure 5. Z89391 84-Pin PLCC Pin Assignments 8 1 Z89391 84-Pin PLCC Zilog 75 VSS 74 PD15 FS1 PD14 UO1 PD13 UO0 PD12 INTO ...
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... PD2 Program Data 2 39 INT1 User Interrupt 1 40 PD3 Program Data 3 41 UI1 User Input 1 42 UI0 User Input 0 DS97DSP0100 Table 4. Z89391 84-Pin PLCC Pin IdentiÞcation Direction No. Symbol Function Input 43 SCLK CODEC Interface Clock In/Output 44 V Power Supply DD Output 45 RD//WR R/W External Bus ...
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Z89321/371/391 16-Bit Digital Signal Processors ABSOLUTE MAXIMUM RATINGS Symbol Description V Supply voltage (*) CC T Storage Temp. STG T Oper. Ambient Temp. A Note: * Voltage on all pins with respect to GND. See Ordering Information. STANDARD TEST CONDITIONS ...
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... Input Low Voltage Output Floating FL Leakage Current Notes: 1. Z89321 and Z89391 only = 5V, ± 5% for 16 MHz operation Z89371 only Z89321 only. Limited availability. Contact Zilog sales office. DC ELECTRICAL CHARACTERISTICS ( 10 Ð40°C to +85°C, unless otherwise specified) ...
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... WHOLD WAIT Hold Time from CLOCK Rise Halt HSET Halt Setup Time to CLOCK Rise HHOLD Halt Hold Time from CLOCK Rise Notes: 1. Z89321 and Z89391 only = 5V ± 5%) 2. Z89371 only ( Z89321 only. Limited availability. Contact Zilog sales office. 12 fclock = 20 1 MHz ...
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Zilog AC ELECTRICAL CHARACTERISTICS = 5V ±10 Ð40°C to +85°C, unless otherwise specified Symbol Clock TCY Clock Cycle Time Tr Clock Rise Time Tf Clock Fall Time CPW Clock Pulse Width I/O DSVALID /DS Valid ...
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Z89321/371/391 16-Bit Digital Signal Processors TIMING DIAGRAMS TCY CLOCK DSVALID /DS EASET EA(2:0) Valid Address Out RD//WR EXT(15:0) CLOCK WAIT /DS EA(2:0) RD//WR EXT(15:0) Figure 8. External (EXT) Bus Read Timing Using WAIT Pin 14 DSHOLD EAHOLD RDHOLD RDSET Data ...
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Z89321/371/391 16-Bit Digital Signal Processors TIMING DIAGRAMS (Continued) TCY CLOCK DSVALID /DS EASET EA(2:0) Valid Address Out EASET RD//WR EXT(15:0) 15 DSHOLD EAHOLD EAHOLD WRHOLD WRVALID Data Out Figure 9. Write Timing ...
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Z89321/371/391 16-Bit Digital Signal Processors TCY CLOCK SSET SCLK FSSET FS0, FS1 TXSET TXD 1 RXD CLOCK INT 0,1,2 INTWidth PROGRAM Fetch N –1 ADDRESS EXECUTE RXHOLD RXSET Figure 10. CODEC Interface Timing TCY ...
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Z89321/371/391 16-Bit Digital Signal Processors TIMING DIAGRAMS (Continued) CLOCK HHOLD HSET HALT CLOCK RSET /RESET RWIDTH INTERNAL RESET EXECUTE Cycle 0 Cycle 1 RD/WR /DS UO0-1 EA0-2 EXT0-15 PA0-15 RAM/ REGISTERS 17 TCY Figure 12. HALT Timing TCY RRISE Cycle ...
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... Reset (0FFCH). Internal ROM is mapped from 0000H to 0FFFH, and the highest location for program is 0FFBH word External Program Memory Space is available on the Z89391. The vector addresses for the Z89391 re- side at FFFCH-FFFFH (Figure 15). Internal Data RAM. The Z89321, 371 and 391 all have in- ternal 512 x 16-bit word data RAM organized as two banks of 256 x 16-bit words each: RAM0 and RAM1 ...
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Zilog FUNCTIONAL DESCRIPTION Instruction Timing. Most instructions are executed in one machine cycle. Long immediate instructions and Jump or Call instructions are executed in two machine cycles. A multiplication or multiplication/accumulate instruction re- quires a single cycle. Specific instruction cycle ...
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Z89321/371/391 16-Bit Digital Signal Processors Hardware Stack. A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses or data. The Call instruction pushes PC+2 onto the stack, and the RET instruction pops the contents of the ...
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Zilog REGISTERS The internal registers are defined below: Register Register DeÞnition P Output of Multiplier, 24-bit X X Multiplier Input, 16-bit Y Y Multiplier Input, 16-bit A Accumulator, 24-bit SR Status Register, 16-bit Pn:b Six Ram Address Pointers, 8-bit each ...
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Z89321/371/391 16-Bit Digital Signal Processors The status register can always be read in its entirety. S15- S10 are set/reset by hardware and can only be read by software. S9-S0 control hardware looping and can be writ- ten by software (Table ...
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Zilog PERIPHERAL OPERATION Disabling Peripherals Disabling a peripheral (CODEC Interface, Counter) allows general-purpose use of the EXT address for the disabled peripheral. If the peripheral is not disabled, the EXT control signals and EXT data are still provided, but transfer ...
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Z89321/371/391 16-Bit Digital Signal Processors CODEC Interface The CODEC Interface provides direct-connect capabilities for standard 8-, 16-bit CODECs. The interface also sup- ports 8-bit PCM, 8-bit PCM with hardware m-law conver- sion (m-law expansion is done in software), 16-bit Linear ...
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Zilog TXD (Serial Output to CODEC) The TXD line provides 8-, 16-, and 64-bit data transfers. Each bit is clocked out of the processor by the rising edge of the SCLK, with the MSB transmitted first. RXD (Serial Input from ...
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Z89321/371/391 16-Bit Digital Signal Processors 5-1 D15 D14 D13 D12 D11 D10 D9 D8 5-2 D15 D14 D13 D12 D11 D10 D9 D8 Figure 22. CODEC Interface Data Registers (Channel 0) 6-1 D15 D14 D13 D12 D11 D10 D9 D8 ...
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Zilog REGISTERS EXT7-1 D15 D14 D13 D12 D11 D10 D9 Note: The timer is an up-counter. Example: EXT7-1 = #%x00D OSC = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz EXT7-1 = #%x80F OSC = 12.288 MHz, SCLK ...
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Z89321/371/391 16-Bit Digital Signal Processors EXT7-2 D15 D14 D13 D12 D11 D10 D9 Figure 25. WSG, SCLK and CODEC Interface Control Register ...
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Zilog A/D Accommodation The CODEC interface can be used for serial A/D or serial D/A transmission. The interface provides the necessary control signals to adapt to many standard serial convert- ers. The low-pass and smoothing filters are necessary for systems ...
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Z89321/371/391 16-Bit Digital Signal Processors Z89321 /371 /391 TXD RXD SCLK FS1 int1_ fs1 fs0 sclk txd rxd 30 VCC MC145505p VDD 16 1 VAG RDD 15 2 Rx0 RCE Txl CCI 12 5 ...
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Zilog 16-Bit Linear CODEC Interface For higher precision transmissions, a 16-bit linear CODEC is used, however, data is not compressed in this mode of transmission. The Z89321 provides accommodation for two channels of 16-bit transmission (Figure 29). int1_ fs1 fs0 ...
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Z89321/371/391 16-Bit Digital Signal Processors Stereo CODEC Interface The Z893XX DSP product family CODEC interface pro- vides direct connection to other CODECs for master or slave modes, supporting 64 bits of transmission data (16 bits right channel, 16 bits left ...
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Zilog int1_ fs1 fs0 sclk txd rxd Figure 32. CODEC Stereo Mode Timing Diagram 16-Bit General-Purpose Timer The 13-bit counter/timer is available for general-purpose use. When the counter counts down to the zero state, an interrupt is received on INT2. ...
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Z89321/371/391 16-Bit Digital Signal Processors ADDRESSING MODES (Continued) EXT4 D15 D14 D13 D12 D11 D10 * Default State ADDRESSING MODES This section discusses the syntax of the addressing modes supported by the DSP assembler. Symbolic Name <pregs> <dregs> (Points to ...
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Zilog There are eight distinct addressing modes for data trans- fer. <pregs>, <hwregs> These two modes are used for sim- ple loads to and from registers within the chip, such as loading to the Accumulator, or loading from a pointer ...
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Z89321/371/391 16-Bit Digital Signal Processors PACKAGE INFORMATION 36 Figure 34. 40-Pin Package Diagram Figure 35. 44-Pin PLCC Package Diagram Zilog DS97DSP0100 ...
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Zilog DS97DSP0100 Figure 36. 44-Pin QFP Package Diagram Figure 37. 84-Pin PLCC Package Diagram Z89321/371/391 16-Bit Digital Signal Processors 37 1 ...
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... F = Plastic QFP Temperature S = 0°C to +70° -40°C to 85°C Example: Z 89321 Z89391 20 MHz 84-Pin PLCC Z8939120VSC Speed MHz MHz Environmental C = Plastic Standard is a Z89321, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow Environmental Flow T emperature Package ...
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Zilog © 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is ...
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Z89321/371/391 16-Bit Digital Signal Processors Zilog DS97DSP0100 ...