MPC8270 MOTOROLA [Motorola, Inc], MPC8270 Datasheet - Page 75

• Manufacturer Part Number: MPC8270
• Description: PowerQUICC II Family Hardware Specifications
• Manufacturer: MOTOROLA [Motorola, Inc]

MOTOROLA
Revision
1.0
2/2004
Date
• Removal of “Advance Information” and “Preliminary.” The MPC8280 is fully qualified.
• Table 1: New
• Figure 1: Modification to note 2
• Section 1.1: Core frequency range is 166–450 MHz
• Addition of ZQ (516 PBGA with Lead spheres) package references
• Table 4: VDD and VCCSYN modified to 1.45–1.60 V
• Note following Table 4: Modified
• Table 5: Addition of note 2 regarding TRST and PORESET (see VIH row of Table 5)
• Table 5: Changed I
• Table 5: Moved QREQ to V
• Table 5: Addition of critical interrupt (CINT) to IRQ5 for V
• Table 6: Addition of Ψ
• Sections 4.1–4.2: New
• Table 7: Modified power values (+ 150mW to each)
• Table 8: Addition of note 2. Changed PCI impedance to 27 Ω.
• Table 9: Changes to sp36b, SP38a, sp38b, sp37a, sp39a, sp40 and sp41
• Table 10: Changes to sp16a, sp18a, sp20 and sp21
• Section 6.2: Addition of Note: CLKIN Jitter and Duty Cycle
• Table 11: Changes to sp13 @ 66 and 83 MHz, sp14 @ 83 MHz
• Table 12: Change to sp30 (data bus signals). Changes to sp33b. Removal of note 2.
• Table 15 through Table 19: Modification of note 1 regarding CPU and CPM Fmin. Modification
• Table 20: Addition of note 1 to TRST (AH3) and PORESET (AG6)
• Table 20: Addition of RXD3 to CPM port pin PB14. Previously omitted.
• Table 20: Addition of critical interrupt (CINT) to B21 and U4. Previously omitted.
• Table 20: Addition of note 5 to ‘No connect’ (AA1, AG4)
• Addition of “Note: Temperature Reflow for the VR Package" on page 58
• Table 22: Addition of note 1 to TRST (F22) and PORESET (B25)
• Table 22: Addition of previously omitted signals that are multiplexed with CPM port pins:
• Table 22: Removal of serial interface 1 (SI1) signals from port pins (see note 2 in Figure 1):
• Table 22: Addition of critical interrupt (CINT) to AC1 and B14. Previously omitted.
• Table 22: Addition of note 5 to ‘No connect’ (E17, C23)
MPC8280 PowerQUICC II™ Family Hardware Specifications
to corresponding values in tables.
PA6—FCC2_UT_RXADDR3
PA7—FCC2_UT_TXADDR3
PA8—FCC2_UT_TXADDR4
PB14—RXD3
PC19—SPICLK
PC22—FCC1_UT_TXPRTY
PC28—FCC2_UT_RXADDR4
PA[6–9], PB[8–17, 20–25], PC[6–7, 10–13], PD[4, 10–13, 16, 23–28]
Table 24. Document Revision History
OL
JT
for 60x signals to 6.0 mA
and note 4
OL
: I
OL
Substantive Changes
= 3.2 mA
OL
(I
Document Revision History
OL
= 6.0mA)
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