CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 32

• Manufacturer Part Number: CP80S54E
• Description: EPROM/ROM-Based 8-Bit Microcontroller Series
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

INCRSZ
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
INT
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
IORAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
IORIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
IOST
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Increment R, Skip if 0
INCRSZ R, d
0
d
R + 1
None
The contents of register ‘R’ are incremented. If ‘d’ is 0 the result is placed in the ACC register.
If ‘d’ is the result is placed back in register ‘R’.
If the result is 0, then the next instruction, which is already fetched, is discarded and a NOP is
executed instead making it a two-cycle instruction.
1(2)
S/W Interrupt
INT
None
002h
None
Interrupt subroutine call. First, return address (PC+1) is pushed onto the stack. The address
002h is loaded into PC bits <9:0>.
2
OR ACC with R
IORAR R, d
0
d
ACC or R
Z
Inclusive OR the ACC register with register ‘R’. If ‘d’ is 0 the result is placed in the ACC
register. If ‘d’ is 1 the result is placed back in register ‘R’.
1
OR Immediate with ACC
IORIA I
0
ACC or I
Z
The contents of the ACC register are OR’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Load IOST Register
IOST R
R = 5 or 6
ACC
None
1
PC + 1
IOST register ‘R’ (R= 5 or 6) is loaded with the contents of the ACC register.
∈
∈
≤
≤
≤
R
[0,1]
R
[0,1]
I
≤
≤
≤
255
63
63
IOST register R
PC
dest, skip if result = 0
Top of Stack,
ACC
dest
CP80S54/56
Rev0.1 Nov 30, 2005
P.32/CP80S54/S56