CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 9

• Manufacturer Part Number: CP80S54E
• Description: EPROM/ROM-Based 8-Bit Microcontroller Series
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

2.1.4 STATUS (Status Register)
This register contains the arithmetic status of the ALU, the RESET status.
If the STATUS Register is the destination for an instruction that affects the Z, DC or C bits, then the write to these
three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits
are not writable. Therefore, the result of an instruction with the STATUS Register as destination may be different
than intended. For example, CLRR STATUS will clear the upper three bits and set the Z bit. This leaves the
STATUS Register as 000u u1uu (where u = unchanged).
C : Carry/borrow bit.
DC : Half carry/half borrow bit.
Z : Zero bit.
GP2:GP0 : General purpose read/write bits.
2.1.5 FSR (Indirect Data Memory Address Pointer)
Bit5:Bit0 : Select registers address in the indirect addressing mode. See 2.1.1 for detail description.
Bit7:Bit6 : Not used. Read as “1”s.
PD : Power down flag bit.
TO : Time overflow flag bit.
03h (r/w)
04h (r/w)
Address
Address
Note : A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRR, RLR)
= 1, the result of a logic operation is zero.
= 0, the result of a logic operation is not zero.
ADDAR, ADDIA
= 1, a carry occurred.
= 0, a carry did not occur.
SUBAR, SUBIA
= 1, a borrow did not occur.
= 0, a borrow occurred.
ADDAR, ADDIA
= 1, a carry from the 4th low order bit of the result occurred.
= 0, a carry from the 4th low order bit of the result did not occur.
SUBAR, SUBIA
= 1, a borrow from the 4th low order bit of the result did not occur.
= 0, a borrow from the 4th low order bit of the result occurred.
= 1, after power-up or by the CLRWDT instruction.
= 0, by the SLEEP instruction.
= 1, after power-up or by the CLRWDT or SLEEP instruction.
= 0, a watch-dog time overflow occurred.
instructions, this bit is loaded with either the high or low order bit of the source register.
STATUS
Name
Name
FSR
GP2
B7
B7
*
GP1
B6
B6
*
GP0
B5
B5
Indirect data memory address pointer
TO
B4
B4
PD
B3
B3
CP80S54/56
B2
B2
Z
Rev0.1 Nov 30, 2005
DC
B1
B1
P.9/CP80S54/S56
B0
B0
C