MC68HC11K0CFN3 MOTOROLA [Motorola, Inc], MC68HC11K0CFN3 Datasheet - Page 40

• Manufacturer Part Number: MC68HC11K0CFN3
• Description: Technical Summary 8-Bit Microcontroller
• Manufacturer: MOTOROLA [Motorola, Inc]

CME —Clock Monitor Enable
FCME —Force Clock Monitor Enable
CR[1:0] —COP Timer Rate Select
COPRST —Arm/Reset COP Timer Circuitry
HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous
RBOOT —Read Bootstrap ROM
SMOD —Special Mode Select
MDA —Mode Select A
40
MOTOROLA
RESET:
RESET:
Refer to NOCOP bit in CONFIG register.
Write $55 (%01010101) to COPRST to arm COP watchdog clearing mechanism. Write $AA
(%10101010) to COPRST to reset COP watchdog. Refer to NOCOP bit in CONFIG register.
*RBOOT, SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode.
Refer to 2 Operating Modes.
Refer to 2 Operating Modes.
Refer to 2 Operating Modes.
CR[1:0]
0 = Clock monitor disabled; slow clocks can be used
1 = Slow or stopped clocks cause clock failure reset
0 = Clock monitor follows the state of the CME bit
1 = Clock monitor circuit is enabled until next reset
0 0
0 1
1 0
1 1
RBOOT*
Bit 7
Bit 7
—
7
0
Selected
Rate
E =
2
2
2
2
15
17
19
21
Table 6 COP Timer Rate Select (Timeout Period Length)
SMOD*
—
6
6
0
6
–0 ms, +16.4 ms
XTAL = 8.0 MHz
MDA*
16.384 ms
65.536 ms
262.14 ms
1.049 sec
Timeout
2.0 MHz
—
5
5
0
5
PSEL4
4
4
0
4
0
PSEL3
XTAL = 12.0 MHz
–0 ms, +10.9 ms
3
3
0
3
0
10.923 ms
43.691 ms
174.76 ms
699.05 ms
Timeout
3.0 MHz
PSEL2
2
2
0
2
1
PSEL1
1
1
0
1
1
XTAL = 16.0 MHz
–0 ms, +8.2 ms
32.768 ms
131.07 ms
524.29 ms
8.192 ms
Timeout
4.0 MHz
M68HC11 K Series
PSEL0
$003A
$003C
MC68HC11KTS/D
Bit 0
Bit 0
0
0
0