MC68HC705SR3 MOTOROLA [Motorola, Inc], MC68HC705SR3 Datasheet - Page 56

• Manufacturer Part Number: MC68HC705SR3
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units
• Manufacturer: MOTOROLA [Motorola, Inc]

8
8.1.2
The index register is an 8-bit register, which can contain the indexed addressing value used to
create an effective address. The index register may also be used as a temporary storage area.
8.1.3
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
8.1.4
The stack pointer is a 16-bit register, which contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to
location $00FF. The stack pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011. These
ten bits are appended to the six least significant register bits to produce an address within the
range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64
locations are exceeded, the stack pointer wraps around and overwrites the previously stored
information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
8.1.5
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just
executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually
tested by a program, and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
Half carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
MOTOROLA
8-2
Increasing
memory
address
Index register (X)
Program counter (PC)
Stack pointer (SP)
Condition code register (CCR)
Freescale Semiconductor, Inc.
Unstack
For More Information On This Product,
CPU CORE AND INSTRUCTION SET
7
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Figure 8-2 Stacking order
Condition code register
Program counter high
Program counter low
Index register
Accumulator
0
Stack
Decreasing
memory
address
MC68HC05SR3
TPG