PEB2080 SIEMENS [Siemens Semiconductor Group], PEB2080 Datasheet - Page 28

• Manufacturer Part Number: PEB2080
• Description: S/T Bus Interface Circuit(SBC)
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Functional Description
NT and LT-S Applications
The 192-kHz transmit bit clock is synchronized to the IOM clock DCL. In the receive direction two
cases have to be distinguished depending whether a bus or a point-to-point operation is
programmed (pin X3:BUS).
Bus Operation
The 192-kHz receive bit clock is identical to the transmit bit clock, shifted by 4.6 s with respect to
the transmit edge. According to CCITT I.430, the receive frame shall be shifted by two bits with
respect to the transmit frame.
Point-to-Point Operation
The 192-kHz receive bit clock is recovered from the receive data stream on the S interface (the
sampling instant for the receive bits is shifted by 3.9 s with respect to the leading edge of the
derived receive clock). According to CCITT I.430, the receive frame can be shifted by 2-8 bits with
respect to the transmit frame at the NT (LT-S) (Other shifts are allowed by SBC (including 0)).
This operation mode should also be used in extended passive bus applications.
E channel handling
For D-channel access collision resolution, the received D bit is in all cases transmitted as the E bit
in the S-frames.
In addition, in the NT mode the echo bit may be made externally available, thus allowing for the
implementation of a star configuration.
TE Application
The transmit and receive bit clocks are derived, with the help of the DPLL, from the S-interface
receive data strem.
The transmit frame is shifted by two bits with respect to the received frame. The output clocks CP,
DCL and FSC are synchronous to the S-interface timing.
Semiconductor Group
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