PEB2447 SIEMENS [Siemens Semiconductor Group], PEB2447 Datasheet
PEB2447
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PEB2447 Summary of contents
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ICs for Communications Memory Time Switch Extended Large MTSXL PEB 2447 Version 1.2 Data Sheet 03.97 T2447-XV12-D2-7600 ...
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PEB 2447 Revision History: Previous Version: Page Page Subjects (major changes since last revision) (in previous (in current Version) Version Register Address Arrangement (new) Edition 03.97 This edition was realized using the software system FrameMaker . Published by ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Memory Time Switch Extended Large MTSXL Version 1.2 1 Overview 1.1 Features • Non blocking time/space switch for 4.096- or 8.192-Mbit/s PCM systems • Device clock 16.384 MHz • Switching 2048 incoming PCM channels ...
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Logic Symbol Figure 1 Functional Symbol 1.3 General Device Overview The Siemens Memory Time Switch Extended Large MTSXL (PEB 2447 capacity expansion of the MTSL (PEB 2047 monolithic CMOS switching device capable of connecting ...
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Pin Configuration (top view IN0 81 IN1 82 IN2 ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Tristate (T) 81 IN0 I 82 IN1 I 83 IN2 I 84 IN3 I 85 IN4 I 86 IN5 I 87 IN6 I 88 IN7 I 89 ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Tristate (T) 16 FS0 I 17 FS1 I 18 FS2 I 19 FS3 I 20 FS4 I 21 FS5 ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Tristate (T) 75 OUT0 O/T 74 OUT1 O/T 73 OUT2 O/T 72 OUT3 O/T 71 OUT4 O/T 70 OUT5 O/T 69 OUT6 O/T 68 OUT7 O/T 65 ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) Tristate (T) 78 TMS I (internal pull-up) 79 TDI I (internal pull-up) 80 TCK I Semiconductor Group Function Test Mode Select: 0 -> 1 transitions on this ...
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Functional Description The MTSXL is a memory time switch device. Operating with a device clock of 16.384 MHz it can connect any of 2048 PCM input channels to any of 2048 output channels. A general block diagram of the ...
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Figure 3 Block Diagram of MTSXL The synchronization of the input and output counters is achieved by a rising edge of the sync pulse SP, which is always sampled with the falling edge of the device clock. Different modes of ...
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During operation of the chip a frame length check is also supplied, which controls correct synchronization by the SP pulse and generates an interrupt in case of lost or achieved synchronization. The unused output ports are tristated by mode selection, ...
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Boundary Scan and TAP Controller 2.3.1 Boundary Scan The MTSXL provides fully IEEE Std. 1149.1 compatible boundary scan support consisting of – a complete boundary scan – a test access port controller (TAP controller) – four dedicated pins (TCK, ...
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Table 2 Boundary Scan Sequence (cont’d) Boundary Scan Pin Number TDI -> Number 100 ...
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Table 2 Boundary Scan Sequence (cont’d) Boundary Scan Pin Number TDI -> Number ...
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Table 2 Boundary Scan Sequence (cont’d) Boundary Scan Pin Number TDI -> Number ...
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TAP Controller The TAP controller implements a state machine defined in the JTAG standard IEEE1149.1. The instruction register of the controller is extended to 4 bits in order to increase the number of instructions. This is necessary for the ...
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The extended TAP controller uses a modified data path: Table 4 Data Path of 4 Bit TAP Controller Instruction Code Input 11xx TDI 00xx BSOUT 0011 BSOUT_ID 01xx TDI2: STAR:STOK (internal) 10xx TDI3: VSS (not used, internal) When TAP_TEST1 / ...
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The TAP controller state machine passes through the different states according to figures Table 6 States of TAP Controller (explanation for figures Controller State Exit2-DR Exit1-DR Shift-DR Pause-DR Select-IR-Scan Update-DR Capture-DR Select-DR-Scan Exit2-IR Exit1-IR ...
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Figure 4 Starting Instruction “TAP_TEST2” (code 0101) Figure 5 Writing Selftest Control Register Semiconductor Group Functional Description 21 PEB 2447 03.97 ...
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Figure 6 Start of Built in Selftest (instruction TAP_TEST1, code 0100) Figure 7 Readout of Selftest Result (after 10240 TCK periods) Note: After the use of the selftest procedure over the P Interface or the boundary scan interface a hardware ...
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Operational Description 3.1 Initialization Procedure For a proper initialization of the MTSXL the following procedure is recommended: First a reset pulse (RES least two CLK clock periods has to be applied. All registers contain now their reset ...
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Typical Write Operation: WR MWDL WR MWDH WR MAAL WR MACH RD STAR; STAR:MAC = 0 3.4 Frame Evaluation If the device is in synchronized state (STAR:PSS = 1) and for example the command “frame evaluation at FS5” (CMDR = ...
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Input Offset and Output Offset Based on the results of the frame evaluation procedures the input offsets can be adjusted by programming ICSR 7..0 corresponding to inputs IN 7..0. If data oversampling is used, the values of ICSR 7..0 ...
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Figure 10 Output Timing The output offset is the same for all output lines and is fixed in register OCSR. Semiconductor Group Operational Description 26 PEB 2447 03.97 ...
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Frame Delay Figure 11 shows a functional description of the Serial Input, Data Memory and Serial Output. Figure 11 Internal Processing of Serial Data In mode 0 for example inputs 0 and 8 are both connected to the input ...
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Figure 12 Internal Control Signals Mode 0 (OCSR = 0) Note: O_SYN is a control signal for the synchronization of RD and WR access to the data memory and not important for the external functionality. O_SYN frequency ...
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If the offset of output time slot to input time slot is greater or equal to the internal delay due to table 7 the transmission of data is within the same frame (frame delay 0). If the offset is smaller ...
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Figure 13 Internal Control Signals Mode 1/3 (OCSR = 0) Semiconductor Group Operational Description 30 PEB 2447 03.97 ...
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Table 8 Time Slot Delay Mode (deduced from figure 13, only Input time slots 0, 2, 4,..) OCS(4: ...
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Detailed Register Description 4.1 Register Address Arrangement Reg. Access Name MODR RD/WR CMDR WR STAR RD ISTA RD MASK WR MACH RD/WR MAAL RD/WR MRDL RD/WR MRDH RD/WR MWDL RD/WR MWDH RD/WR ICSR RD/WR (15:0) OSCR RD/WR TSTR RD/WR ...
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Mode Register (MODR) Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 PSB 0 PSB PCM Stand By; a logical 0 switches the PCM interface outputs to high impedance. MD1 … MD0 Mode; these bits define the ...
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Command Register (CMDR) Access in demultiplexed P-interface mode: Write, address: Reset Value: Bit 7 0 FSAD2 FSAD1 FSAD0 FSAD2..0 Frame Synchronization signal Address Address of the chosen FS signal evaluated by ...
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Status Register (STAR) Access in demultiplexed P-interface mode: Read, address: Reset value: Bit 7 0 FSAD2 FSAD1 FSAD0 FSAD2..0 Frame Synchronization signal Address: see CMDR. MAC Memory Access Active; an indirect memory access is active, if this bit is ...
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Interrupt Status Register (ISTA) Access in demultiplexed P-interface mode: Read, address: Reset value: Bit FEC Frame Evaluation Completed; the indirect register FER contains a valid offset and can be read. PC Procedure Completed; the procedure started ...
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Mask Register (MASK) Access in demultiplexed P-interface mode: Write, address: Reset value: Bit logical 1 disables the corresponding interrupt as described in ISTA from activating the INT pin. A masked interrupt (bit set to “1”) ...
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Memory Access Address Register Low (MAAL) Access in a demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 MA7 MA6 MA7..0 Memory Address bits the complete memory address is the concatenation of MA10..0. If the value ...
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Memory Read Data Register Low (MRDL) Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 MRD7 MRD6 MRD5 MRD4 MRD3 MRD2 MRD1 MRD0 MRD7..0 Memory Read Data values (bits 7 to 0); see MRDH; 4.10 Memory Read ...
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Memory Write Data Register High (MWDH) Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit MWD11..8 Memory Write Data values (bits write memory access the values to transfer are written ...
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Input Clock Shift Register Bank ICSR (15:0) Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 ADRS 0 ADSR Add Shift Register; a three bit shift register is inserted into the corresponding input(s), resulting in an additional ...
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Output Clock Shift Register (OSCR) Access in demultiplexed P-interface mode: Read/write, address: Reset value: Bit 7 VN1 VN0 VN1..0 Version Number according to the table below: (read only) Table 14 Version Number OCS4..0 Output Clock Shift; ...
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Frame Evaluation Register Low (FERL) Access in a demultiplexed P-interface mode: Read, address: Reset value: Bit 7 FEV7 FEV6 FEV7..0 Frame Evaluation Values (bits 7 to 0); refer to FERH; 4.17 Frame Evaluation Register High (FERH) Access in demultiplexed ...
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Electrical Characteristics Table 16 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Supply voltage Input voltage Output voltage Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to conditions ...
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Table 18 Capacitances ° Parameter Input capacitance Output capacitance I/O capacitance AC Characteristics Ambient temperature under bias range, Inputs are driven at 2.4 V for a logical 1 ...
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Table 19 P Interface Timing Parameters Parameter Address setup time to WR, RD Address hold time from WR pulse width Data output delay from RD Data float from RD RD control interval WR pulse width Data setup time ...
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Figure 16 P Write Cycle Figure 17 Demultiplexed Address Timing Figure 18 Interrupt Timing Semiconductor Group Electrical Characteristics 47 PEB 2447 03.97 ...
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Table 20 PCM Interface Characteristics Parameter Clock period Clock period low Clock period high Frame setup time Frame hold time Serial data input setup time Serial data input hold time PCM serial data output delay time Semiconductor Group Electrical Characteristics ...
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Figure 19 AC Characteristics at the PCM Interface Semiconductor Group Electrical Characteristics 49 PEB 2447 03.97 ...
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Table 21 Boundary Scan Timing Parameter Test clock period Test clock period low Test clock period high TMS setup time to TCK TMS hold time from TCK TDI setup time to TCK TDI hold time from TCK TDO delay from ...
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Package Outlines P-MQFP-100-2 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 51 PEB 2447 Package Outlines Dimensions in ...