FDC37B72X_07 SMSC [SMSC Corporation], FDC37B72X_07 Datasheet - Page 19

• Manufacturer Part Number: FDC37B72X_07
• Description: 128 Pin Enhanced Super I/O Controller with ACPI Support
• Manufacturer: SMSC [SMSC Corporation]

PS/2 Model 30 Mode
BIT 0 nDRIVE SELECT 2
The DS2 disk interface is not supported. (Always
1)
BIT 1 nDRIVE SELECT 3
The DS3 disk interface is not supported. (Always
1)
BIT 2 WRITE GATE
Active high status of the latched WGATE output
signal. This bit is latched by the active going edge
of WGATE and is cleared by the read of the DIR
register.
BIT 3 READ DATA
Active high status of the latched RDATA output
signal. This bit is latched by the inactive going
RESET
COND.
nDRV2
N/A
7
nDS1
6
1
nDS0
5
1
WDATA
F/F
4
0
19
edge of RDATA and is cleared by the read of the
DIR register.
BIT 4 WRITE DATA
Active high status of the latched WDATA output
signal. This bit is latched by the inactive going
edge of WDATA and is cleared by the read of the
DIR register. This bit is not gated with WGATE.
BIT 5 nDRIVE SELECT 0
Active low status of the DS0 disk interface output.
BIT 6 nDRIVE SELECT 1
Active low status of the DS1 disk interface output.
BIT 7 nDRV2
Active low status of the DRV2 disk interface input,
this is not supported. (Always 1).
RDATA
F/F
3
0
WGATE
F/F
2
0
nDS3
1
1
nDS2
0
1