FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 113

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

UART Power Management
Direct power management is controlled by CR22.
Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B4
and B5. When set, these bits allow the following
auto power management operations:
1.
2.
Note:
Exit Auto Powerdown
The transmitter exits powerdown on a write to the
XMIT buffer. The receiver exits auto powerdown
when RXDx changes state.
Parallel Port
Direct power management is controlled by CR22.
Refer to CR22 for more information.
Auto Power Management is enabled by CR23-B3.
When set, this bit allows the ECP or EPP logical
parallel port blocks to be placed into powerdown
when not being used.
The EPP logic is in powerdown under any of the
following conditions:
1.
2.
The ECP logic is in powerdown under any of the
following conditions:
The transmitter enters auto powerdown when
the transmit buffer and shift register are
empty.
The receiver enters powerdown when the
following conditions are all met:
A.
B.
EPP is not enabled in the configuration
registers.
EPP is not selected through ecr while in ECP
mode.
Receive FIFO is empty
The receiver is waiting for a start bit.
While in powerdown the Ring Indicator
interrupt is still valid and transitions when
the RI input changes.
115
1.
2
Exit Auto Powerdown
The parallel port logic can change powerdown
modes when the ECP mode is changed through
the ecr register or when the parallel port mode is
changed through the configuration registers.
V
This chip requires a (TBD) MicroAmp battery
supply (V
registers. These registers retain the contents of
the general purpose registers and wake-up event
registers.
also battery backed up. Note: The configuration
of the Consumer IR wake-up functionality is not
battery backed-up.
V
The FDC37B78x requires a 25 mA trickle supply
(V
programmable wake-up events in the Soft Power
Management logic, SCI, PME and SMI interfaces
when V
intended to provide wake-up capabilities on
standby current, V
V
interface, the CIR run-time registers, the PME
configuration registers, and the PME interface.
The V
signal to initialize certain components.
wakeup event registers and related logic are
battery backed-up to retain the configuration of
the wakeup events upon a power loss (i.e., V
0 V and V
a V
BAT
TR
TR
TR
BAT
Support
)
ECP is not enabled in the configuration
registers.
selected through ecr while in ECP mode.
SPP, PS/2 Parallel port or EPP mode is
Support
powers the Consumer IR receiver, IR
TR
POR.
CC
to
pin generates a V
TR
BAT
is removed. If the FDC37B78x is not
The RTC and CMOS registers are
provide
= 0 V). These registers are reset on
) to provide battery backed up
TR
can be connected to V
sleep
TR
current
Power-on-Reset
for
CC
the
CC
All
=
.