FDC37B787QF SMSC [SMSC Corporation], FDC37B787QF Datasheet - Page 128

• Manufacturer Part Number: FDC37B787QF
• Description: Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
• Manufacturer: SMSC [SMSC Corporation]

KEYBOARD ISA INTERFACE
The FDC37B78x ISA interface is functionally
compatible with the 8042-style host interface. It
consists of the D0-7 data bus; the nIOR, nIOW
Note 1: These registers consist of three separate 8 bit registers. Status, Data/Command Write and Data
Read.
Keyboard Data Write
This is an 8 bit write only register. When written,
the C/D status bit of the status register is cleared
to zero and the IBF bit is set.
Keyboard Data Read
This is an 8 bit read only register. If enabled by
"ENABLE FLAGS", when read, the KIRQ output is
cleared and the OBF flag in the status register is
cleared.
AUXOBF1 must be cleared in software.
ISA ADDRESS
OUT DBB
0x60
0x64
8042 INSTRUCTION
If not enabled, the KIRQ and/or
nIOW
0
1
0
1
Set OBF, and, if enabled, the KIRQ output signal goes high
TABLE 57 - ISA I/O ADDRESS MAP
nIOR
Table 58 - Host Interface Flags
1
0
1
0
BLOCK
KDATA
KDATA
KDCTL
KDCTL
130
and the Status register, Input Data register, and
Output Data register. TABLE 57 shows how the
interface decodes the control signals. In addition
to the above signals, the host interface includes
keyboard and mouse IRQs.
Keyboard Command Write
This is an 8 bit write only register. When written,
the C/D status bit of the status register is set to
one and the IBF bit is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the
description of the Status Register for more
information.
CPU-to-Host Communication
The FDC37B78x CPU can write to the Output
Data register via register DBB. A write to this
register automatically sets Bit 0 (OBF) in the
Status register. See Table 58.
Keyboard Data Read
Keyboard Status Read
Keyboard Data Write (C/D=0)
Keyboard Command Write (C/D=1)
FLAG
FUNCTION (NOTE 1)