FDC37B80X SMSC [SMSC Corporation], FDC37B80X Datasheet - Page 99

• Manufacturer Part Number: FDC37B80X
• Description: PC98/99 Compliant Enhanced Super I/O Controller with Keyboard/Mouse Wake-Up
• Manufacturer: SMSC [SMSC Corporation]

The interrupt generated is ISA friendly in that it
must pulse the interrupt line low, allowing for
interrupt sharing.
following the interrupt event, the interrupt line is
tri-stated so that other interrupts may assert.
An interrupt is generated when:
1. For DMA transfers: When serviceIntr is 0,
2. For Programmed I/O:
3. When nErrIntrEn is 0 and nFault transitions
4. When ackIntEn is 1 and the nAck signal
FIFO Operation
The
configuration registers. All data transfers to or
from the parallel port can proceed in DMA or
Programmed I/O (non-DMA) mode as indicated
by the selected mode.
selecting the Parallel Port FIFO mode or ECP
dmaEn is 1 and the DMA TC is received.
a.
b.(1)
from high to low or when nErrIntrEn is set
from 1 to 0 and nFault is asserted.
transitions from a low to a high.
FIFO
When serviceIntr is 0, dmaEn is 0,
direction
writeIntrThreshold or more free bytes in
the FIFO.
generated when serviceIntr is cleared
to
writeIntrThreshold or more free bytes in
the FIFO.
threshold
0
FIFO does not cross the
threshold.
When serviceIntr is 0, dmaEn
is 0, direction is 1 and there
are readIntrThreshold or more
bytes in the FIFO.
interrupt is generated when
serviceIntr is cleared to 0
whenever
readIntrThreshold
bytes in the FIFO.
is
whenever
After a brief pulse low
Also, an interrupt is
0
is
The FIFO is used by
set
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99
Parallel Port Mode. (FIFO test mode will be
addressed separately.) After a reset, the FIFO
is disabled. Each data byte is transferred by a
Programmed I/O cycle or PDRQ depending on
the selection of DMA or Programmed I/O mode.
The following paragraphs detail the operation of
the FIFO flow control.
<threshold> ranges from 1 to 16.
parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
A low threshold value (i.e. 2) results in longer
periods of time between service requests, but
requires faster servicing of the request for both
read and write cases. The host must be very
responsive to the service request. This is the
desired case for use with a "fast" system. A
high value of threshold (i.e. 12) is used with a
"sluggish" system by affording a long latency
period after a service request, but results in
more frequent service requests.
DMA TRANSFERS
DMA transfers are always to or from the
ecpDFifo, tFifo or CFifo.
standard PC DMA services. To use the DMA
transfers, the host first sets up the direction and
state as in the programmed I/O case. Then it
programs the DMA controller in the host with the
desired count and memory address. Lastly it
sets dmaEn to 1 and serviceIntr to 0. The ECP
requests DMA transfers from the host by
activating the PDRQ pin. The DMA will empty
or fill the FIFO using the appropriate direction
and mode. When the terminal count in the DMA
controller is reached, an interrupt is generated
and serviceIntr is asserted, disabling DMA. In
order to prevent possible blocking of refresh
requests dReq shall not be asserted for more
than 32 DMA cycles in a row.
enabled directly by asserting nPDACK and
addresses need not be valid. PINTR is
generated when a TC is received. PDRQ must
not be asserted for more than 32 DMA cycles in
a row. After the 32nd cycle, PDRQ must be
kept unasserted until nPDACK is deasserted for
In these descriptions,
DMA utilizes the
The FIFO is
The