FDC37C665GT_07 SMSC [SMSC Corporation], FDC37C665GT_07 Datasheet
FDC37C665GT_07
Related parts for FDC37C665GT_07
FDC37C665GT_07 Summary of contents
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High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers 5 Volt Operation Floppy Disk Available on Parallel Port Pins 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible to the 82077AA ...
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Supports Four Floppy Drives Directly (Standard and Enhanced Modes) Ÿ General Purpose 11 Bit Address Decoder FEATURES ...................................................................................................................................... 1 GENERAL DESCRIPTION................................................................................................................ 3 PIN CONFIGURATION...................................................................................................................... 4 DESCRIPTION OF PIN FUNCTIONS ................................................................................................ 5 FUNCTIONAL DESCRIPTION ........................................................................................................ 22 SUPER I/O REGISTERS ...........................................................................................................22 HOST ...
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The SMSC FDC37C665GT and FDC37C666GT Advanced High Performance Parallel Port Super I/O Floppy Disk Controller ICs utilize SMSC's proven SuperCell technology for increased product reliability and functionality. The FDC37C665GT is optimized motherboard applications FDC37C666GT is oriented towards controller card applications. ...
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PIN CONFIGURATION nRTS1 82 nCTS1 83 nDTR1 84 nRI1 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL HOST PROCESSOR INTERFACE 48-51 Data Bus 0-7 D0-D7 53-56 44 nI/O Read nIOR 45 nI/O Write nIOW 46 Address Enable AEN 28-34 I/O Address A0-A9 41-43 52 FDC DMA FDRQ Request 36 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 38 Serial Port IRQ4 Interrupt Request Primary Serial PSPIRQ Port Interrupt 37 Serial Port IRQ3 Interrupt Request Secondary Serial SSPIRQ Port Interrupt 40 Floppy FINTR Controller Interrupt Request BUFFER TYPE DESCRIPTION O24 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 39 Parallel Port PINTR1 Interrupt Request 1 57 Reset RST 16 nRead Disk Data nRDATA 10 nWrite nWGATE Gate 9 nWrite nWDATA Data 11 nHead nHDSEL Select BUFFER TYPE DESCRIPTION O24 This ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 7 nDirection nDIR Control 8 nStep Pulse nSTEP 17 nDisk Change nDSKCHG 4,3 nDrive Select nDS0,1 O,1 98 nDrive Select 2 nDS2 nDrive Select 3 nDS3 PDIR PDIR 97 nDrive Select 3 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 1 Density Select DENSEL 14 nWrite nWRTPRT Protected 13 nTrack 00 nTR0 12 nIndex nINDEX 19,18 Data Rate 0, DRATE0, Data Rate 1 DRATE1 19,18 Media ID0, Media ID1 78,88 Receive Data ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 81 nRequest to nRTS1 Send Parallel Port PCF1 Configuration Control 91 nRequest to nRTS2 Send Secondary Serial S2CF0 Port Configuration Control BUFFER TYPE DESCRIPTION O4 Active low Request to Send output for ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 83 nData Terminal nDTR1 Ready IDE IDECF Configuration Control 93 nData Terminal nDTR2 Ready Secondary Serial S2CF1 Port Configuration Control 1 89 Transmit Data 2 TXD2 FDCCF BUFFER TYPE DESCRIPTION O4 Active ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 82,92 nClear to Send nCTS1, nCTS2 80,90 nData Set Ready nDSR1, nDSR2 85,87 nData Carrier nDCD1, Detect nDCD2 BUFFER TYPE DESCRIPTION I Active low Clear to Send inputs for primary and secondary ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 84,86 nRing Indicator nRI1, nRI2 94 Drive 2 DRV2 nADRx nADRx Parallel Port PINTR2 Interrupt Request 2 ECPEN PARALLEL PORT INTERFACE BUFFER TYPE DESCRIPTION I Active low Ring Indicator input for primary ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 73 nPrinter Select nSLCTIN Input 74 nInitiate Output nINIT 76 nAutofeed nAUTOFD Output 77 nStrobe Output nSTROBE 61 Busy BUSY 62 nAcknowledge nACK BUFFER TYPE DESCRIPTION OD24 This active low output selects ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 60 Paper End PE 59 Printer Selected SLCT Status 75 nError nERR 71-68 Port Data PD0-PD7 66-63 100 IOCHRDY IOCHRDY 23 nIDE Low Byte nIDEENLO Enable S1CF1 BUFFER TYPE DESCRIPTION I Another ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 24 nIDE High Byte nIDEENHI Enable S1CF0 25 nHard Disk Chip nHDCS0 Select IDEACF 26 nHard Disk Chip nHDCS1 Select FACF 27 nI/O 16 Bit nIOCS16 Indicator nHDACK BUFFER TYPE DESCRIPTION O8 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 22 IDE Data Bit 7 IDED7 58 Power Good PWRGD nGame Port nGAMECS Chip Select PADCF 20 CLOCK 1 X1/CLK1 21 CLOCK 2 X2/CLK2 BUFFER TYPE DESCRIPTION I/O24 IDE data bit 7 ...
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DESCRIPTION OF PIN FUNCTIONS PIN NO. NAME SYMBOL 15,72 Power V CC 6,47, Ground GND 67,95 Note 1: These active low open drain outputs select motor drives 0-3. In non-ECP modes, four drives can be supported directly. These motor enable ...
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BUFFER TYPE DESCRIPTIONS BUFFER TYPE I/O24 Input/output sink source. O24 Output sink source. OD24 Output sink. OD24P Open drain sink source. OP24 Output sink; ...
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PWRGD Vcc (2) Vss (4) (FDC37C665GT only) (FDC37C666GT only) POWER MANAGEMENT nIOR nIOW ADDRESS BUS AEN A0-A9 DO-D7 FDRQ nDACK HOST CPU TC INTERFACE IRQ3 IRQ4 PROPRIETARY PINTR 82077 COMPATIBLE PINTR2 FINTR RESET PDRQ CLOCK GEN PDACK nINDEX nTRK0 A10 ...
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FDC37C665GT FDC36C666GT CLOCK 1 24 MHz CRYSTAL 20 pF FIGURE 2 - SUGGESTED 24 MHz OSCILLATOR CIRCUIT CLOCK ...
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SUPER I/O REGISTERS The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, IDE, serial and parallel ports can be moved ...
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FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an ...
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STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins, PS/2 Mode 7 INT nDRV2 PENDING RESET 0 COND. BIT 0 DIRECTION Active high status ...
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PS/2 Model 30 Mode 7 INT DRQ PENDING RESET 0 COND. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicating direction a logic "1" outward. BIT 1 WRITE PROTECT Active high status of ...
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STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins, in PS/2 and Model PS/2 Mode RESET 1 1 COND. BIT 0 MOTOR ENABLE 0 ...
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PS/2 Model 30 Mode 7 6 nDRV2 nDS1 RESET N/A 1 COND. BIT 0 nDRIVE SELECT 2 Active low status of the DS2 disk interface output. BIT 1 nDRIVE SELECT 3 Active low status of the DS3 disk interface output. ...
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DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also 7 6 MOT MOT EN3 EN2 RESET 0 0 COND. BIT 0 and 1 DRIVE SELECT These ...
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TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE This register is included for 82077 software compatability. The robust digital data separator used in the FDC37C665GT does not require its characteristics modified for tape support. The contents of this register are not ...
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Table 7 - External Drive Decode - Normal DIGITAL OUTPUT REGISTER Bit 7 Bit 6 Bit 5 Bit ...
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Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits are a high impedance. DB7 DB6 REG 3F3 Tri-state Tri-state Enhanced Floppy Mode 2 (OS2) Register 3F3 for ...
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Table 11 - Drive Type ID Digital Output Register Bit 1 Bit Register 3F3 - Drive Type ID Bit 5 Bit 4 CR6 - Bit 1 CR6 - Bit 0 ...
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DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only used to program the data rate, amount of write precompensation, power down status, and software reset. data rate is programmed Configuration Control Register (CCR) ...
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Table 13 - Data Rates DRATESEL DATA RATE 1 0 MFM Mbps 0 0 500 Kbps 250 Kbps 0 1 300 Kbps 150 Kbps 1 0 250 Kbps 125 Kbps MAIN STATUS REGISTER Address 3F4 READ ONLY ...
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DATA REGISTER (FIFO) Address 3F5 READ/WRITE All command parameter information, disk data and result status are transferred between the host processor and the floppy disk controller through the Data Register. Data transfers are governed by the RQM and DIO bits ...
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DIGITAL INPUT REGISTER (DIR) Address 3F7 READ ONLY This register is read-only in all modes. PC-AT Mode 7 6 DSK CHG RESET N/A N/A COND. BIT UNDEFINED The data bus outputs will remain in ...
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Model 30 Mode 7 6 DSK 0 CHG RESET N/A 0 COND. BITS DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 13 for the settings corresponding to the individual data ...
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CONFIGURATION CONTROL REGISTER (CCR) Address 3F7 WRITE ONLY PC/AT and PS/2 Modes 7 6 RESET N/A N/A COND. BIT 0 and 1 DATA RATE SELECT 0 and 1 These bits determine the data rate of the floppy controller. See Table ...
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STATUS REGISTER ENCODING During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment ...
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Table 18 - Status Register 1 BIT NO. SYMBOL NAME 7 EN End of Cylinder Data Error 4 OR Overrun/ Underrun Data 1 NW Not Writable 0 MA Missing Address Mark DESCRIPTION The ...
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Table 19 - Status Register 2 BIT NO. SYMBOL NAME Control Mark 5 DD Data Error in Data Field 4 WC Wrong Cylinder Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. ...
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BIT NO. SYMBOL NAME Write Protected Track Head Address 1,0 DS1,0 Drive Select RESET There are three sources of system reset on the FDC: the RESET pin of the FDC37C665GT, ...
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PS/2 mode - (IDENT low, MFM high) This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the DOR becomes a "don't care", (FINTR and DRQ are always valid), TC and DENSEL become active low. ...
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A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then ...
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If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector hardware TC was received. The only difference between ...
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COMMAND SET/DESCRIPTIONS Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, ...
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Table 21 - Description of Command Symbols SYMBOL NAME GAP Alters Gap 2 length when using Perpendicular Mode. GPL Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). H/HDS Head Address ...
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Table 21 - Description of Command Symbols SYMBOL NAME MT Multi-Track Selector N Sector Size Code NCN New Cylinder Number ND Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number POLL Polling Disable PRETRK Precompensation Start Track Number R Sector ...
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Table 21 - Description of Command Symbols SYMBOL NAME SK Skip Flag When set to 1, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors ...
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PHASE R Command W MT MFM Execution Result INSTRUCTION SET Table 22 - Instruction Set READ DATA DATA BUS D5 ...
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PHASE R Command W MT MFM Execution Result READ DELETED DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DATA DATA BUS ...
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PHASE R Command W MT MFM Execution Result WRITE DELETED DATA DATA BUS ...
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PHASE R Command W 0 MFM Execution Result READ A TRACK DATA BUS ...
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PHASE R Command W MT MFM Execution Result PHASE R Command Result VERIFY ...
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PHASE R Command W 0 MFM Execution for W Each Sector Repeat Result FORMAT A TRACK DATA BUS ...
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PHASE R Command Execution PHASE R Command Result R R PHASE R Command --- SRT --- W ------ HLT ------ RECALIBRATE ...
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PHASE R Command Result R PHASE R Command Execution PHASE R Command EIS ...
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PHASE R Command W 1 DIR PHASE R/W D7 Command W 0 Execution Result ---- SRT ---- LOCK R 0 EIS EFIFO POLL R RELATIVE SEEK ...
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PHASE R Command W 0 MFM Execution Result READ ID DATA BUS HDS DS1 DS0 ...
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PHASE R Command PHASE R Command W ----- Invalid Codes ----- Result R PHASE R/W D7 Command W LOCK Result returned if the last command that was issued was ...
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DATA TRANSFER COMMANDS All of the Read Data, Write Data and Verify type commands use the same parameter bytes and return the same results information, the only difference being the coding of bits 0-4 in the first byte. An implied ...
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If the FDC detects a pulse on the nINDEX pin twice without finding the specified sector (meaning that the diskette's index hole passes through index detect logic in the drive twice), the FDC sets the IC code in Status Register ...
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Read Deleted Data This command is the same as the Read Data command, only it operates on sectors that contain a Deleted Data Address Mark at the beginning of a Data Field. Table 26 - Skip Bit vs. Read Deleted ...
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FINAL SECTOR MT HEAD TRANSFERRED TO HOST Less than EOT 0 0 Equal to EOT Less than EOT 1 Equal to EOT Less than EOT 0 1 Equal to EOT Less than EOT 1 Equal to EOT NC: No Change, ...
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Definition of DTL when and when N does not = 0 Write Deleted Data This command is almost the same as the Write Data command except that a Deleted Data Address Mark is written at the beginning ...
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Format A Track The Format command allows an entire track to be formatted. After a pulse from the IDX pin is detected, the FDC starts writing data on the disk including gaps, address marks, ID fields, and data fields per ...
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Table 29 - Typical Values for Formatting FORMAT SECTOR SIZE 128 128 512 FM 1024 2048 4096 5.25" ... Drives 256 256 512* MFM 1024 2048 4096 ... 128 FM 256 3.5" 512 Drives 256 MFM 512** 1024 GPL1 = ...
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CONTROL COMMANDS Control commands differ from commands in that no data transfer takes place. Three commands generate an interrupt when complete: Read ID, Recalibrate, and Seek. The other control commands do not generate an interrupt. Read ID The Read ID ...
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Note that if implied seek is not enabled, the read and write commands should be preceded by: 1) Seek command - Step to the proper track 2) Sense Interrupt Status command Terminate the Seek command 3) Read ID - Verify ...
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Head Load signal goes high and the read/write operation starts. Table 31 - Drive Control Delays (ms) HUT 1M 500K 0 128 256 112 224 F 120 240 ...
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PRETRK - Pre-Compensation Number. Programmable from track 0 to 255. Defaults to track 0. A "00" selects track 0; "FF" selects track 255. Version The Version command checks to see if the controller is an enhanced type or the older ...
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Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command. Perpendicular Mode The Perpendicular Mode command should be issued prior to executing Read/Write/Format commands that ...
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When both GAP and WGATE bits of the PERPENDICULAR MODE COMMAND are both programmed to "0" (Conventional mode), then D0, D1, D2, D3, and D4 can be programmed independently to "1" for that ...
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This byte reflects the value of the LOCK bit set by the command byte. ENHANCED DUMPREG The DUMPREG command is designed to support system run-time diagnostics application software development and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR ...
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PARALLEL PORT FLOPPY DISK CONTROLLER In this mode, the Floppy Disk Control signals are available on the parallel port pins. When this mode is selected, the parallel port is not available. There are two modes of operation, PPFD1 and PPFD2. ...
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Table 33 - FDC Parallel Port Pins CONNECTOR PIN # CHIP PIN # ...
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The FDC37C665GT and FDC37C666GT incorporate two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable ...
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The following section describes the operation of the registers. RECEIVE BUFFER REGISTER (RB) Address Offset = 0H, DLAB = 0, READ ONLY This register holds the received incoming data byte. Bit 0 is the least significant bit, which is transmitted ...
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Bit 2 Setting this bit to a logic "1" clears all bytes in the XMIT FIFO and resets its counter logic to 0. The shift register is not cleared. This bit is self- clearing. Bit 3 Writting to this bit ...
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Table 35 - Interrupt Control Table FIFO INTERRUPT MODE IDENTIFICATION ONLY REGISTER BIT BIT BIT BIT PRIORIT LEVEL Highest Second ...
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LINE CONTROL REGISTER (LCR) Address Offset = 3H, DLAB = 0, READ/WRITE This register contains the format information of the serial line. The bit definitions are: Bits 0 and 1 These two bits specify the number of bits in each ...
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Bit 0 This bit controls the Data Terminal Ready (nDTR) output. When bit 0 is set to a logic "1", the nDTR output is forced to a logic "0". When bit logic "0", the nDTR output is ...
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FIFO it applies to. This error is indicated when the associated character is at the top of the FIFO. Bit 3 Framing Error (FE). Bit 3 indicates that the received character did not ...
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Bit 0 Delta Clear To Send (DCTS). Bit 0 indicates that the nCTS input to the chip has changed state since the last time the MSR was read. Bit 1 Delta Data Set Ready (DDSR). Bit 1 indicates that the ...
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FIFO INTERRUPT MODE OPERATION When the RCVR FIFO and receiver interrupts are enabled (FCR bit 0 = "1", IER bit 0 = "1"), RCVR interrupts occur as follows: A. The receive data available interrupt will be issued when the FIFO ...
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In this mode, the user's program will check RCVR and XMITTER status via the LSR. LSR definitions for the FIFO Polled Mode are as follows: Bit 0=1 as long as there is one byte in the RCVR FIFO. Bits 1 ...
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Table 37 - Reset Function Table REGISTER/SIGNAL Interrupt Enable Register RESET Interrupt Identification Reg. RESET FIFO Control RESET Line Control Reg. RESET MODEM Control Reg. RESET Line Status Reg. RESET MODEM Status Reg. RESET TXD1, TXD2 RESET INTRPT (RCVR errs) ...
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Table 38 - Register Summary for an Individual UART Channel REGISTER ADDRESS* REGISTER NAME ADDR = 0 Receive Buffer Register (Read Only) DLAB = 0 ADDR = 0 Transmitter Holding Register (Write DLAB = 0 Only) ADDR = 1 Interrupt ...
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Table 38 - Register Summary for an Individual UART Channel (continued) BIT 2 BIT 3 Data Bit 2 Data Bit 3 Data Bit 2 Data Bit 3 Enable Enable Receiver Line MODEM Status Status Interrupt Interrupt (ELSI) (EMSI) Interrupt ID ...
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NOTES ON SERIAL PORT OPERATION FIFO MODE OPERATION: GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. TX AND RX FIFO OPERATION The Tx portion of the UART transmits data through TXD ...
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The FDC37C665GT and FDC37C666GT incorporate one IBM XT/AT compatible parallel port. The FDC37C665GT and FDC37C666GT support the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer FDC37C665GT ...
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Table 39 - Parallel Port Connector HOST CONNECTOR PIN NUMBER 1 77 2-9 71-68, 66- (1) = Compatible Mode (3) = High Speed Mode ...
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IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES DATA PORT ADDRESS OFFSET = 00H The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the Data ...
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BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. BIT 1 AUTOFD - AUTOFEED This bit is inverted and output onto the nAUTOFD output. A logic 1 causes the printer to generate a line ...
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EPP DATA PORT 3 ADDRESS OFFSET = 07H The EPP Data Port 3 is located at an offset of '07H' from the base address. Refer to EPP DATA PORT 0 for a description of operation. This register is only available ...
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Peripheral asserts nWAIT, indicating to the host that any hold time requirements have been satisfied and acknowledging the termination of the cycle. 9. Chip may modify nWRITE and nPDATA in preparation for the next cycle. EPP 1.9 Read The ...
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EPP 1.7 Write The timing for a write operation (address or data) is shown in timing diagram EPP 1.7 Write Data or Address cycle. IOCHRDY is driven active low when nWAIT is active low during the EPP cycle. This can ...
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Table 40 - EPP Pin Descriptions EPP NAME TYPE EPP SIGNAL nWRITE nWrite PD<0:7> Address/Data I/O INTR Interrupt nWAIT nWait nDATASTB nData Strobe nRESET nReset nADDRSTB nAddress Strobe PE Paper End SLCT Printer Selected Status nERR nError PDIR Parallel Port ...
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EXTENDED CAPABILITIES PARALLEL PORT ECP provides a number of advantages, some of which are listed below. The individual features are explained in greater detail in the remainder of this section. Ÿ High performance half-duplex forward and reverse channel Ÿ Interlocked ...
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ISA IMPLEMENTATION STANDARD This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP must meet the requirements contained in this section or the port will not be supported by Microsoft. For a ...
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Table 41 - ECP Pin Descriptions NAME TYPE nStrobe O During write operations nStrobe registers data or address into the slave on the asserting edge (handshakes with Busy). PData 7:0 I/O Contains address or data or RLE data. nAck I ...
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Register Definitions The register definitions are based on the standard IBM addresses for LPT. standard printer ports are supported. The additional registers attach to an upper bit decode of the standard LPT port definition to Table 42 - ECP Register ...
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DATA and ecpAFifo PORT ADDRESS OFFSET = 00H Modes 000 and 001 (Data Port) The Data Port is located at an offset of '00H' from the base address. The data register is cleared at initialization by RESET. WRITE operation, the ...
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Refer to the description of the interrupt under Operation, Interrupts. BIT 5 DIRECTION If mode=000 or mode=010, this bit has no effect and the direction is always out regardless of ...
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Data bytes are always read from the head of tFIFO regardless of the value of the direction bit. For example if 44h, 33h, 22h is written to the FIFO, then reading the tFIFO will return 44h, 33h, 22h in the ...
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Table 44 - Extended Control Register R/W 000: Standard Parallel Port mode . In this mode the FIFO is reset and common collector drivers are used on the control lines (nStrobe, nAutoFd, nInit and nSelectIn). Setting the direction bit will ...
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OPERATION Mode Switching/Software Control Software will execute P1284 negotiation and all operation prior to a data transfer phase under programmed I/O control (mode 000 or 001). Hardware provides an automatic control line handshake, moving data between the FIFO and the ...
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Command/Data ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features implemented by allowing the transfer of normal 8-bit data or 8-bit commands. When in the forward direction, normal data is transferred ...
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PS/2 mode using program control of the control signals. Interrupts The interrupts are enabled by serviceIntr in the ecr register. serviceIntr = 1 Disables the DMA and all of the service interrupts. serviceIntr = ...
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A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. DMA TRANSFERS DMA transfers are always to or from the ...
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Programmed I/O - Transfers from the FIFO to the Host In the reverse direction an interrupt occurs when serviceIntr is 0 and readIntrThreshold bytes are available in the FIFO this time the FIFO is full it can be ...
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INTEGRATED DRIVE ELECTRONICS INTERFACE The IDE interface enables hard disks with embedded controllers (AT and XT interfaced to the host processor. The following definitions are for reference only. registers are not implemented FDC37C665GT and FDC37C666GT. Access to these ...
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COMMAND RESTORE (RECALIBRATE) SEEK READ SECTOR WRITE SECTOR FORMAT TRACK READ VERIFY DIAGNOSE SET PARAMETERS Bit definitions: r: specifies the step rate to be used for the command set, 16 bit DMA used for the ...
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ADDR R/W D15 D14 D13 D12 D11 000H R/W ADDR R 001H R BB CRC 001H W 002H R/W 003H R/W 004H R/W 005H R/W 006H R 007H R BSY RDY WF 007H W AT ...
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ADDR R 3F6H/ R BSY RDY WF 376H 3F6H/ W RESERVED 376H 3F7H nWG nHS3 377H 3F7H 377H MISCELLANEOUS AT REGISTERS DRQ CD HS3EN ADPTR RESET nHS2 nHS1 ...
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The configuration of the FDC37C665GT within the user system is selected through software selectable configuration registers. The different configurations of the FDC37C666GT can be selected through a combination of jumper options and software. FDC37C665GT CONFIGURATION REGISTERS The configuration registers are ...
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ENTER CONFIGURATION MODE ;-----------------------------' MOV DX,3F0H MOV AX,055H ;use 044H for FDC37C666GT CLI ; disable interrupts OUT DX,AL OUT DX,AL STI ; enable interrupts ;-----------------------------. ; CONFIGURE REGISTERS CR0-CRx | ;-----------------------------' MOV DX,3F0H MOV AL,00H OUT DX,AL ; ...
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Table 46 - FDC37C665GT Configuration Registers Default DB7 DB6 3BH CR0 VALID 9FH CR1 LOCK CRx COM3, 4 ADDR DCH CR2 UART2 PWR UART2 EN 78H CR3 ADRx/ IDENT DRV2 EN/ PINTR 00H CR4 (RESERVED) EPP Type 00H CR5 (RESERVED) ...
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CR0 This register can only be accessed when the FDC is in the Configuration Mode and after the CSR has been initialized to 00H. The default BIT NO. BIT NAME 0 IDE ENABLE 1 IDE AT/XT 2 RESR 3 FDC ...
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CR1 This register can only be accessed when the FDC is in the Configuration Mode and after the BIT NO. BIT NAME 0,1 Parallel Port Address 2 Parallel Port Power 3 Parallel Port Mode 4 IRQ Polarity 5,6 COM3,4 7 ...
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CR2 This register can only be accessed when the FDC is in the Configuration Mode and after the BIT NO. BIT NAME 0,1 UART 1 Address Select 2 UART 1 Enable 3 UART 1 Power down 4,5 UART 2 Address ...
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CR3 This register can only be accessed when the FDC is in the Configuration Mode and the BIT NO. BIT NAME 0 RESERVED Reserved - Read as zero 1 Enhanced Bit 1 Floppy Mode Drive Opt ...
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Table 51 - Drive Option 1 and 2 DATA RATE REGISTER SETTINGS KB/sec DRATE DRATE SEL 1 SEL 0 1000 1 500 0 300 0 250 1 1000 1 500 0 300 0 250 CONFIG. ...
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CR4 This register can only be accessed when the FDC is in the Configuration Mode and the Table 52 - CR4 - Parallel and Serial Extended Setup Register BIT NO. BIT NAME 1,0 Parallel Port Extended Modes 2,3 Parallel Port ...
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CR5 This register can only be accessed when the FDC is in the Configuration Mode and the Table 53 - CR5- Floppy Disk and IDE Extended Setup Register BIT NO. BIT NAME 0 FDC Secondary 1 IDE Secondary 2 FDC ...
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CR6 This register can only be accessed when the FDC is in the Configuration Mode and after the CSR has been initialized to 06H. The default value of this register after power up is FFH. This register holds the floppy ...
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BIT NO FDC37C666GT Hardware Configuration The FDC37C666GT hardware configuration can select or deselect the parallel, serial, FDC PCF1 PCF0 ECPEN Table 54 - CRF ...
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S1CF1 S1CF0 S2CF1 S2CF0 IDECF IDEACF FDCCF FACF 0 0 Floppy Disabled, Configuration registers at 3F0H and 3F1H and allow ...
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FDC37C666GT Software Configuration - Differences from FDC37C665GT All software configuration options available for the FDC37C665GT are available FDC37C666GT except for those selected by the hardware configuration pins. The options set by hardware configuration in the FDC37C666GT that cannot be changed ...
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OPERATIONAL DESCRIPTION MAXIMUM GUARANTEED RATINGS* Operating Temperature Range......................................................................................... 0 Storage Temperature Range..........................................................................................-55 Lead Temperature Range (soldering, 10 seconds) .................................................................... +325 Positive Voltage on any pin, with respect to Ground ................................................................V Negative Voltage on any pin, with respect to Ground.................................................................... -0.3V ...
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PARAMETER SYMBOL Input Current PWRGD I/O24 Type Buffer Low Output Level V High Output Level Output Leakage O24 Type Buffer Low Output Level V High Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage OD24P Type Buffer ...
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PARAMETER SYMBOL O4 Type Buffer Low Output Level High Output Level Output Leakage O8 Type Buffer Low Output Level High Output Level Output Leakage Supply Current Active Supply Current Standby ChiProtect (SLCT, PE, BUSY, nACK, nERROR) Backdrive (nSTROBE, nAUTOFD, nINIT,nSLCTIN) ...
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TIMING DIAGRAMS A0-A9, AEN, nIOCS16 t1 t6 nIOR t4 DATA (D0-D7) PD0-PD7, nERR, PE, nSLCT, ACK, BUSY FINTR nIOR/nIOW PINTR Parameter t1 A0-A9, AEN, nIOCS16 Set Up to nIOR Low t2 nIOR Width t3 A0-A9, AEN, nIOCS16 Hold from nIOR ...
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A0-A9, AEN, nIOCS16 t1 nIOW DATA (D0-D7) FINTR PINTR Parameter t1 A0-A9, AEN, nIOCS16 Set Up to nIOW Low t2 nIOW Width t3 A0-A9, AEN, nIOCS16 Hold from nIOW High Data Set Up Time to nIOW High t4 t5 Data ...
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AEN FDRQ, PDRQ t1 nDACK t14 t6 nIOR t5 or nIOW DATA (DO-D7) TC Parameter t1 nDACK Delay Time from FDRQ High t2 DRQ Reset Delay from nIOR or nIOW t3 FDRQ Reset Delay from nDACK Low t4 nDACK Width ...
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RESET Parameter t1 RESET Width FIGURE 7 - RESET TIMING CLOCK (CLK1) t1 Parameter t1 Clock Rise Time (VIN = 0.4 to 3.0) t2 Clock Fall Time (VIN = 3.0 to 0.4) t3 Clock Period t4 Clock Active (High ...
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MTR0-3 (AT Mode timing only) Parameter t1 nDIR Set Up to nSTEP Low t2 nSTEP Active Time Low t3 nDIR Hold Time After nSTEP t4 nSTEP Cycle Time t5 nDS0-3 ...
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IRQx nCTSx, nDSRx, nDCDx t2 IRQx nIOW IRQx nIOR nRIx Parameter t1 nRTSx, nDTRx Delay from nIOW t2 IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from nIOR (Leading Edge) t4 IRQx Inactive Delay ...
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AEN, nIOCS16 A0- nIDEENLO, nIDEENHI, nGAMECS, HDCSx IDED7 t10 nIOR t4 DB7 DB7 nIOW t7 IDED7 Parameter t1 nIDEENLO, nIDEENHI, nGAMECS, nHDCSx Delay from AEN, IOCS16 t2 nIDEENLO, nIDEENHI, nGAMECS, nHDCSx Delay from A0-A9 t3 IDED7 Hold Time ...
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PD0-PD7 t1 nIOW nINIT, nSTROBE. nAUTOFD, SLCTIN nACK t2 PINTR (SPP) PINTR (ECP or EPP Enabled) nFAULT (ECP) nERROR (ECP) PINTR Parameter t1 PD0-7, nINIT, nSTROBE, nAUTOFD Delay from nIOW t2 PINTR Delay from nACK, nFAULT t3 PINTR Active Low ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 IOCHRDY t13 t22 t20 nWRITE t1 PD<7:0> t16 t3 t14 nDATAST nADDRSTB nWAIT t21 PDIR Parameter t1 nIOW Asserted to PDATA Valid t2 nWAIT Asserted to nWRITE Change t3 nWRITE to Command Asserted t4 ...
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A0-A10 t19 IOR SD<7:0> t8 IOCHRDY t24 t23 PDIR t9 t21 nWRITE t2 t25 PD<7:0> t28 t26 t1 t14 DATASTB ADDRSTB t15 nWAIT Timing parameter table for the EPP Data or Address Read Cycle is found on page 144. FIGURE ...
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Parameter t1 PDATA Hi-Z to Command Asserted t2 nIOR Asserted to PDATA Hi-Z t3 nWAIT Deasserted to Command Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t6 PDATA Hi-Z to nWAIT Deasserted t7 PDATA Valid ...
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A0-A10 SD<7:0> t17 t8 nIOW t10 t20 IOCHRDY t13 nWRITE t1 PD<7:0> t16 t3 nDATAST nADDRSTB nWAIT PDIR Parameter t1 nIOW Asserted to PDATA Valid t2 Command Dessserted to nWRITE Change t3 nWRITE to Command t4 nIOW Deasserted to Command ...
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A0-A10 t19 nIOR SD<7:0> IOCHRDY nWRITE PD<7:0> t23 nDATASTB nADDRSTB nWAIT PDIR Parameter t2 nIOR Deasserted to Command Deasserted t3 nWAIT Asserted to IOCHRDY Deasserted t4 Command Deasserted to PDATA Hi-Z t5 Command Asserted to PDATA Valid t8 ...
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ECP PARALLEL PORT TIMING Parallel Port FIFO (Mode 101) The standard parallel port is run at or near the peak 500Kbytes/sec allowed in the forward direction using DMA. The state machine does not examine nAck and begins the next transfer ...
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The timing for the dynamic driver change is specified in the IEEE 1284 Extended Capabilities Port Protocol and ISA PDATA nSTROBE BUSY Parameter t1 DATA Valid to nSTROBE Active t2 ...
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PDATA<7:0> nSTROBE t6 BUSY Parameter t1 nAUTOFD Valid to nSTROBE Asserted t2 PDATA Valid to nSTROBE Asserted t3 BUSY Deasserted to nAUTOFD Changed t4 BUSY Deasserted to PDATA Changed t5 nSTROBE Asserted to BUSY Asserted t6 ...
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PDATA<7:0> t1 nACK t4 nAUTOFD Parameter t1 PDATA Valid to nACK Asserted t2 nAUTOFD Deasserted to PDATA Changed t3 nACK Asserted to nAUTOFD Deasserted t4 nACK Deasserted to nAUTOFD Asserted t5 nAUTOFD Asserted to nACK Asserted t6 nAUTOFD Deasserted to ...
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0.10 A1 -C- MILLIMETERS DIM MIN MAX MIN A 2.80 3.15 .110 A1 0.1 0.45 .004 A2 2.57 2.87 .101 D 23.4 24.15 .921 D1 19.9 20.1 .783 E 17.4 18.15 .685 E1 13.9 14.1 ...
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ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright © 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, ...