FDC37C665GT_07 SMSC [SMSC Corporation], FDC37C665GT_07 Datasheet - Page 122

• Manufacturer Part Number: FDC37C665GT_07
• Description: High-Performance Multi-Mode Parallel Port Super I/O Floppy Disk Controllers
• Manufacturer: SMSC [SMSC Corporation]

CR2
This register can only be accessed when the
FDC is in the Configuration Mode and after the
BIT NO.
0,1
4,5
2
3
6
7
UART 1 Address
Select
UART 1 Enable
UART 1 Power
down
UART 2 Address
Select
UART 2 Enable
UART 2 Power
down
BIT NAME
These bits select the Primary Serial Port Address.
1 0
0 0
0 1
1 0
1 1
A high level on this bit, enables the Primary Serial Port (Default).
A high level on this bit, allows normal operation of the Primary
Serial Port (Default). A low level on this bit places the Primary
Serial Port into Power Down Mode.
These bits select the Secondary Serial Port Address.
5 4
0 0
0 1
1 0
1 1
A high level on this bit enables the Secondary Serial Port
(Default). A low level on this bit disables the Secondary Serial
Port.
A high level on this bit, allows normal operation of the Secondary
Serial Port (Default). A low level on this bit places the Secondary
Serial Port into Power Down Mode.
A low level on this bit disables the Primary Serial Port.
COM Port
COM2
COM Port
COM1
COM1
COM3
COM4
COM2
COM3
COM4
Table 49 - CR2
122
CSR has been initialized to 02H. The default
value of this register after power up is DCH.
3F8H (Default)
2F8H
(Refer to CR1, bits 5,6)
(Refer to CR1, bits 5,6)
3F8H
2F8H (Default)
(Refer to CR1, bits 5,6)
(Refer to CR1, bits 5,6)
ADDRESS
ADDRESS
DESCRIPTION