MC68HC901P MOTOROLA [Motorola, Inc], MC68HC901P Datasheet - Page 29

• Manufacturer Part Number: MC68HC901P
• Description: Multi-Function Peripheral
• Manufacturer: MOTOROLA [Motorola, Inc]

Interrupt Structure
4.3.2 Interrupt Pending Registers (IPRA, IPRB)
When an interrupt is received on an enabled channel, the corresponding interrupt pending
bit is set in interrupt pending register A or B (IPRA or IPRB). In a vectored interrupt scheme,
this bit will be cleared when the processor acknowledges the interrupting channel and the
MFP responds with a vector number. In a polled interrupt system, the interrupt pending
registers must be read to determine the interrupting channel, and then the interrupt pending
bit is cleared by the interrupt handling routine without performing an interrupt acknowledge
sequence.
GPIP7-GPIP6 — General Purpose Interrupt Pending
Timer A — Timer A Interrupt Pending
Receiver Buffer Full — Receiver Buffer Full Interrupt Pending
Receiver Error — Receiver Buffer Full Interrupt Pending
Transmitter Buffer Empty — Transmitter Buffer Interrupt Pending
Transmitter Error — Transmitter Error Interrupt Pending
Timer B — Timer B Interrupt Pending
4-6
IPRA REGISTER
RESET
FIELD
ADDR
BIT
1 = Pending.
0 = Cleared.
1 = Pending.
0 = Cleared.
1 = Pending.
0 = Cleared.
1 = Pending.
0 = Cleared.
1 = Pending.
0 = Cleared.
1 = Pending.
0 = Cleared.
1 = Pending.
0 = Cleared.
GPIP7
7
0
GPIP6
6
0
TIMER A
MC68HC901 USER’S MANUAL
5
0
BUFFER
FULL
RCV
4
0
$0B
ERROR
RCV
3
0
BUFFER
EMPTY
XMIT
2
0
ERROR
XMIT
1
0
MOTOROLA
TIMER B
0
0