MC68HC908AB32 MOTOROLA [Motorola, Inc], MC68HC908AB32 Datasheet - Page 146

• Manufacturer Part Number: MC68HC908AB32
• Description: HCMOS Microcontroller Unit
• Manufacturer: MOTOROLA [Motorola, Inc]

Clock Generator Module (CGM)
9.6.2 PLL Bandwidth Control Register (PBWC)
Technical Data
146
NOTE:
Address:
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. See
Bits [3:0] — Unimplemented bits
The PLL bandwidth control register does the following:
Reset:
Read:
Write:
the other. During the transition, CGMOUT is held in stasis. See
Base Clock Selector
the BCS bit.
These bits provide no function and always read as 1.
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Freescale Semiconductor, Inc.
For More Information On This Product,
1 = CGMOUT driven by CGMVCLK/2
0 = CGMOUT driven by CGMXCLK/2
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
In manual operation, forces the PLL into acquisition or tracking
mode.
Figure 9-7. PLL Bandwidth Control Register (PBWC)
$001D
AUTO
Bit 7
0
Clock Generator Module (CGM)
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9.4.3 Base Clock Selector
= Unimplemented
LOCK
6
0
ACQ
Circuit. Reset and the STOP instruction clear
5
0
XLD
4
0
Circuit.
3
0
0
MC68HC908AB32
2
0
0
1
0
0
MOTOROLA
—
Rev. 1.0
Bit 0
9.4.3
0
0