SC26C198C1A PHILIPS [NXP Semiconductors], SC26C198C1A Datasheet - Page 11

• Manufacturer Part Number: SC26C198C1A
• Description: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
every 22 Sclk cycles. New arbitration values presented to the
arbitration block during an arbitration cycle will be evaluated in the
next arbitration cycle.
For sources other than receiver and transmitters the user may set
the high order bits of an interrupt source’s bid value, thus tailoring
the relative priority of the interrupt sources. The priority of the
receivers and transmitters is controlled by the fill level of their
respective FIFOs. The more filled spaces in the RxFIFO the higher
the bid value; the more empty spaces in the TxFIFO the higher its
priority. Channels whose programmable high order bits are set will
be given interrupt priority higher than those with zeros in their high
order bits , thus allowing increased flexibility. The transmitter and
receiver bid values contain the character counts of the associated
FIFOs as high order bits in the bid value. Thus, as a receiver’s
RxFIFO fills, it bids with a progressively higher priority for interrupt
service. Similarly, as empty space in a transmitter’s TxFIFO
increases, its interrupt arbitration priority increases.
IACKN Cycle, Update CIR
When the host CPU responds to the interrupt, it will usually assert
the IACKN signal low. This will cause the OCTART to generate an
IACKN cycle in which the condition of the interrupting device is
determined. When IACKN asserts, the last valid interrupt number is
captured in the CIR. The value captured presents most of the
important details of the highest priority interrupt at the moment the
IACKN (or the ”Update CIR” command) was asserted.
The Octal UART will respond to the IACKN cycle with an interrupt
vector. The interrupt vector may be a fixed value, the content of the
Interrupt Vector Register, or ,when ”Interrupt Vector Modification is
enabled via ICR, it may contain codes for the interrupt type and/or
interrupting channel. This allows the interrupt vector to steer the
interrupt service directly to the proper service routine. The interrupt
value captured in the CIR remains until another IACKN cycle occurs
or until an ”Update CIR” command is given to the OCTART. The
interrupting channel and interrupt type fields of the CIR set the
current ”interrupt context” of the OCTART. The channel component
of the interrupt context allows the use of Global Interrupt Information
registers that appear at fixed positions in the register address map.
For example, a read of the Global RxFIFO will read the channel B
RxFIFO if the CIR interrupt context is channel b receiver. At another
time read of the GRxFIFO may read the channel D RxFIFO (CIR
holds a channel D receiver interrupt) and so on. Global registers
exist to facilitate qualifying the interrupt parameters and for writing to
and reading from FIFOs without explicitly addressing them.
The CIR will load with x’00 if IACKN or Update CIR is asserted when
the arbitration circuit is NOT asserting and interrupt. In this
condition there is no arbitration value that exceeds the threshold
value.
Polling
Many users prefer polled to interrupt driven service where there are
a large number of fast data channels and/or the host CPU’s other
interrupt overhead is low. The Octal UART is functional in this
environment.
The most efficient method of polling is the use of the ”update CIR”
command (with the interrupt threshold set to zero) followed by a
read of the CIR. This dummy write cycle will perform the same CIR
capture function that an IACKN falling edge would accomplish in an
interrupt driven system. A subsequent read of the CIR, at the same
address, will give information about an interrupt, if any. If the CIR
contains 0s, no interrupt is awaiting service. If the value is
non–zero, the fields of the CIR may be decoded for type, channel
1995 May 1
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
346
and character count information. Optionally, the global interrupt
registers may be read for particular information about the interrupt
status or use of the global RxD and TxD registers for data transfer
as appropriate. The interrupt context will remain in the CIR until
another update CIR command or an IACKN cycle is initiated by the
host CPU occurs. The CIR loads with x’00 if Update CIR is asserted
when the arbitration circuit has NOT detected arbitration value that
exceeds the threshold value.
Traditional methods of polling status registers may also be used.
They of course are less efficient but give the most variable and
quickest method of changing the order in which interrupt sources
are evaluated and interrogated.
Enabling and Activating Interrupt sources
An interrupt source becomes enabled when its interrupt capability is
set by writing to the Interrupt Mask Register, IMR. An interrupt
source can never generate an IRQN or have its ”bid” or interrupt
number appear in the CIR unless the source has been enabled by
the appropriate bit in an IMR.
An interrupt source is active if it is presenting its bid to the interrupt
arbiter for evaluation. Most sources have simple activation
requirements. The watch-dog timer, break received, Xon/Xoff or
Address Recognition and change of state interrupts become active
when the associated events occur and the arbitration value
generated thereby exceeds the threshold value programmed in the
ICR (Interrupt Control Register).
The transmitter and receiver functions have additional controls to
modify the condition upon which the initiation of interrupt ”bidding”
begins: the TxINT and RxINT fields of the MR0 and MR2 registers.
These fields can be used to start bidding or arbitration when the
RxFIFO is not empty, 50% full, 75% full or 100% full. For the
transmitter it is not full, 50% empty, 75% empty and empty.
Example: To increase the probability of transferring the contents of a
nearly full RxFIFO, do not allow it to start bidding until 50% or 75%
full. This will prevent its relatively high priority from winning the
arbitration process at low fill levels. A high threshold level could
accomplish the same thing, but may also mask out low priority
interrupt sources that must be serviced. Note that for fast channels
and/or long interrupt latency times using this feature should be used
with caution since it reduces the time the host CPU has to respond
to the interrupt request before receiver overrun occurs.
Setting Interrupt Priorities
The bid or interrupt number presented to the interrupt arbiter is
composed of character counts, channel codes, fixed and
programmable bit fields. The interrupt values are generated for
various interrupt sources as shown in the table below: The value
represented by the bits 9 to 3 in the table below are compared
against the value represented by the “Threshold. The “Threshold”
,bits 6 to 0 of the ICR (Interrupt Control Register), is aligned such
that bit 6 of the threshold is compared to bit 9 of the interrupt value
generated by any of the sources. When ever the value of the
interrupt source is greater than the threshold the interrupt will be
generated.
The channel number arbitrates only against other channels. The
threshold is not used for the channel arbitration. This results in
channel D having the highest arbitration number. The decreasing
order is H to A. If all other parts of an arbitration are equal then the
channel number will determine which channel will dominate in the
arbitration process
.
SC26C198 SC68C198
SC26L198 SC68L198
Product specification