SC26C198C1A PHILIPS [NXP Semiconductors], SC26C198C1A Datasheet - Page 21

• Manufacturer Part Number: SC26C198C1A
• Description: Octal UART with TTL compatibility at 3.3V and 5V supply voltages
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 9. Command Register Code
Commands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space.
Table 10. SR – Channel Status Register
SR[7] – Received Break
This bit indicates that an all zero character of the programmed
length has been received without a stop bit. Only a single FIFO
position is occupied when a break is received; further entries to the
FIFO are inhibited until the RxD line returns to the marking state for
at least one half bit time (two successive edges of the internal or
external 1x clock). When this bit is set, the change in break bit in
the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break
condition, as defined above, is detected. The break detect circuitry
is capable of detecting breaks that originate in the middle of a
received character. However, if a break begins in the middle of a
character, it must last until the end of the next character in order for
it to be detected.
SR[6] – Framing Error (FE)
This bit, when set, indicates that a stop bit was not detected when
the corresponding data character in the FIFO was received. The
stop bit check is made in the middle of the first stop bit position.
SR[5] – Parity Error (PE)
This bit is set when the ’with parity’ or ’force parity’ mode is
programmed and the corresponding character in the FIFO was
received with incorrect parity. In the special ’wake up mode’, the
parity error bit stores the received A/D bit.
SR[4] – Overrun Error (OE)
This bit, when set, indicates that one or more characters in the
received data stream have been lost. It is set upon receipt of a new
character when the RxFIFO is full and a character is already in the
receive shift register waiting for an empty FIFO position. When this
1995 May 1
Received
Break
0 – No
1 – Yes
Channel Command
Octal UART with TTL compatibility at 3.3V
and 5V supply voltages
Bit 7
CR[7:3]
00000
00001
00010
00100
00101
01000
01001
01010
00011
00110
00111
01011
01100
01101
01110
Code
01111
Framing Error
0 – No
1 – Yes
Bit 6
Reset Break Change Interrupt
Negate RTSN (I/O2 or I/O1)
Block Error Status configure
Assert RTSN (I/O2 or I/O1)
Set time–out mode on
Set time–out mode off
Begin Transmit Break
End Transmit Break
Reset Error Status
Reset Transmitter
Parity
Error
0 – No
1 – Yes
Reset Receiver
Description
Command
Reserved
Reserved
Reserved
Reserved
Channel
Bit 5
NOP
Overrun Error
0 – No
1 – Yes
Bit 4
Channel Command
356
TxEMT
0 – No
1 – Yes
occurs, the character in the receive shift register (and its break
detect, parity error and framing error status, if any) is lost. This bit is
cleared by a reset error status command.
SR[3] – Transmitter Empty (TxEMT)
This bit is set when the transmitter underruns, i.e., both the TxFIFO
and the transmit shift register are empty.
It is set after transmission of the last stop bit of a character, if no
character is in the TxFIFO awaiting transmission. It is reset when
the TxFIFO is loaded by the CPU, or when the transmitter is
disabled.
SR[2] – Transmitter Ready (TxRDY)
This bit, when set, indicates that the TxFIFO is ready to be loaded
with a character. This bit is cleared when the TxFIFO is loaded by
the CPU and is set when the last character is transferred to the
transmit shift register. TxRDY is reset when the transmitter is
disabled and is set when the transmitter is first enabled, e.g.,
characters loaded in the TxFIFO while the transmitter is disabled will
not be transmitted.
SR[1] – RxFIFO Full (RxFULL)
This bit is set when a character is transferred from the receive shift
register to the receive FIFO and the transfer causes the FIFO to
become full, i.e., all sixteen RxFIFO positions are occupied. It is
reset when the CPU reads the RxFIFO and that read leaves one
empty byte position. If a character is waiting in the receive shift
register because the RxFIFO is full, RxFULL is not reset until the
second read of the RxFIFO since the waiting character is
immediately loaded to the RxFIFO.
CR[7:3]
10000
10001
10010
10011
10100
10101
10110
11000
11001
11010
Code
10111
11011
11100
11101
11110
11111
Bit 3
TxRDY
0 – No
1 – Yes
Bit 2
Gang Load Xon Character Registers DC1 *
Gang Load Xoff Character Registers DC3 *
SC26C198 SC68C198
Gang Write Xon Character Registers *
Gang Write Xoff Character Registers *
SC26L198 SC68L198
Cancel Transmit X Char command
Reset Address Recognition Status
Reset All UART channel registers
Xoff Resume Command
RxFULL
0 – No
1 – Yes
Host Xoff Command
Reset Device *
Transmit Xon
Transmit Xoff
Bit 1
Description
Command
Reserved
Reserved
Reserved
Reserved
Channel
Product specification
RxRDY
0 – No
1 – Yes
Bit 0