AT89C51CC02CA-TDSUM ATMEL [ATMEL Corporation], AT89C51CC02CA-TDSUM Datasheet - Page 70

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AT89C51CC02CA-TDSUM

Manufacturer Part Number
AT89C51CC02CA-TDSUM
Description
Enhanced 8-bit Microcontroller with CAN Controller and Flash
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
Watchdog Programming
70
AT/T89C51CC02
The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the
WDT duration.
Table 50. Machine Cycle Count
To compute WD Timeout, the following formula is applied:
Note:
Find Hereafter computed Timeout values for f
Table 51. Timeout Computation
S2
0
0
0
0
1
1
1
1
S2
0
0
0
0
1
1
1
1
Svalue represents the decimal value of (S2 S1 S0)
F T i m e O u t
S1
0
0
1
1
0
0
1
1
S1
0
0
1
1
0
0
1
1
=
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6
×
S0
0
1
0
1
0
1
0
1
2
W D X
S0
2
0
1
0
1
0
1
0
1
X
F o s c
f
OSC
2
131.07 ms
262.14 ms
524.29 ms
16.38 ms
32.77 ms
65.54 ms
(
1.05 s
2.10 s
2
=12 MHz
14
OSC
×
2
XTAL = 12 MHz in X1 mode
S v a l u e
)
f
Machine Cycle Count
OSC
196.56 ms
393.12 ms
786.24 ms
12.28 ms
24.57 ms
49.14 ms
98.28 ms
1.57 s
=16MHz
2
2
2
2
2
2
2
2
14
15
17
18
19
20
21
16
- 1
- 1
- 1
- 1
- 1
- 1
- 1
- 1
f
OSC
4126J–CAN–05/06
157.28 ms
314.56 ms
629.12 ms
19.66 ms
39.32 ms
78.64 ms
9.82 ms
1.25 s
=20 MHz

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