HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 615

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

13.2.3
Note: * Only 0 can be written, to clear the flag.
RSTCSR is an 8-bit readable/writable * register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal.
RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal
reset signal caused by overflows.
Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details
Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed
(changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer
mode.
Bit 7
WOVF
0
1
Bit 6—Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the chip if
TCNT overflows during watchdog timer operation.
Bit 6
RSTE
0
1
Note: * The modules within the chip are not reset, but TCNT and TCSR within the WDT are reset.
Bit
Initial value :
R/W
see section 13.2.4, Notes on Register Access.
Reset Control/Status Register (RSTCSR)
Description
Cleared by reading RSTCSR when WOVF = 1, then writing 0 to WOVF
Set when TCNT overflows (changes from H'FF to H'00) during watchdog timer
operation
Description
[Clearing condition]
[Setting condition]
Reset signal is not generated if TCNT overflows *
Reset signal is generated if TCNT overflows
:
:
R/(W) *
WOVF
7
0
RSTE
R/W
6
0
R/W
—
5
0
—
—
1
4
Rev.4.00 Sep. 07, 2007 Page 585 of 1210
—
—
3
1
—
—
2
1
REJ09B0245-0400
—
—
1
1
(Initial value)
(Initial value)
—
—
0
1