HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 709

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The operation sequence is as follows.
[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start
[3] With the smart card interface, the data line then returns to the high-impedance state. The data
[4] The receiving station carries out a parity check.
[5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data
Block Transfer Mode: The operation sequence in block transfer mode is as follows.
[1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull-
[2] The transmitting station starts transfer of one frame of data. The data frame starts with a start
[3] With the smart card interface, the data line then returns to the high-impedance state. The data
[4] The receiving station carries out a parity check, but does not output an error signal even if an
[5] The transmitting station proceeds to transmit the next data frame.
up resistor.
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
line is pulled high with a pull-up resistor.
If there is no parity error and the data is received normally, the receiving station waits for
reception of the next data.
If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level)
to request retransmission of the data. After outputting the error signal for the prescribed length
of time, the receiving station places the signal line in the high-impedance state again. The
signal line is pulled high again by a pull-up resistor.
frame.
If it does receive an error signal, however, it returns to step [2] and retransmits the data in
which the error occurred.
up resistor.
bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp).
line is pulled high with a pull-up resistor.
error has occurred. Since subsequent receive operations cannot be carried out if an error
occurs, the error flag must be cleared to 0 before the parity bit for the next frame is received.
Rev.4.00 Sep. 07, 2007 Page 679 of 1210
REJ09B0245-0400