HD6412332 RENESAS [Renesas Technology Corp], HD6412332 Datasheet - Page 795

• Manufacturer Part Number: HD6412332
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first
Note 7: Write Pulse Width
Note: Use a (z3) µs write pulse for additional
Program Data Operation Chart
Number of Writes (n)
2. Verify data is read in 16-bit (W) units.
3. Even bits for which programming has been completed in the 128-byte
4. A 128-byte area for storing program data, a 128-byte area for storing
5. A write pulse of (z1) or (z2) μs should be applied according to the progress
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 22.2.6, Flash Memory Characteristics.
Additional program data
Original Data
Write pulse application subroutine
Reprogram data area
Wait (z1) μs or (z2) μs or (z3) μs
Program data area
address written to must be H'00 or H'80. A 128-byte data transfer must
be performed even if writing fewer than 128 bytes; in this case, H'FF
data must be written to the extra addresses.
programming loop will be subjected to additional programming if they fail
the subsequent verify operation.
reprogram data, and a 128-byte area for storing additional program data
should be provided in RAM. The contents of the reprogram data and
additional program data areas are modified as programming proceeds.
of programming. See note 7 for the pulse widths. When the additional program
data is programmed, a write pulse of (z3) μs should be applied. Reprogram data X' stands for reprogram data to which a write pulse has been applied.
area (128 bytes)
Clear PSU bit in FLMCR1
programming.
(D)
Set PSU bit in FLMCR1
Sub-routine write pulse
0
1
Clear P bit in FLMCR1
(128 bytes)
(128 bytes)
1000
Set P bit in FLMCR1
998
999
10
11
12
13
1
2
3
4
5
6
7
8
9
.
.
.
RAM
Disable WDT
Enable WDT
Wait (α) μs
Wait (β) μs
Wait (y) μs
End sub
Verify Data
(V)
0
1
0
1
Write Time (z) μs
Reprogram Data
*6
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
.
.
.
(X)
Figure 19.14 Program/Program-Verify Flowchart
1
0
1
*6
*5 *6
*6
*6
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
Increment address
Comments
NG
Store 128-byte program data in program
data area consecutively to flash memory
additional program data area in RAM to
Write 128-byte data in RAM reprogram
Transfer reprogram data to reprogram
Additional program data computation
H'FF dummy write to verify address
Transfer additional program data to
Sequentially write 128-byte data in
data area and reprogram data area
Additional Program Data Operation Chart
Reprogram data computation
additional program data area
(z3 µs additional write pulse)
Clear SWE bit in FLMCR1
Clear PV bit in FLMCR1
Reprogram
Set SWE bit in FLMCR1
Set PV bit in FLMCR1
Data (X')
Start of programming
End of programming
Read data = verify
(z1) μs or (z2) μs
Read verify data
data verification
0
1
flash memory
Wait (x) μs
completed?
Write Pulse
Write pulse
Wait (γ) μs
Wait (ε) μs
Wait (η) μs
Wait (θ) μs
data area
128-byte
6 ≥ n ?
6 ≥ n ?
m = 0?
m = 0
n = 1
data?
Start
OK
Verify Data
OK
Rev.4.00 Sep. 07, 2007 Page 765 of 1210
OK
OK
OK
Sub-routine-call
(V)
0
1
0
1
Program Data (Y)
NG
NG
NG
NG
Additional
*6
0
1
*6
*4
*1
See note 7 for pulse width
*6
*6
*6
*2
*4
*3
*4
*6
*1
*6
m = 1
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Clear SWE bit in FLMCR1
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
Programming failure
Wait (θ) μs
n ≥ N?
OK
Comments
*6
REJ09B0245-0400
NG
n ← n + 1
*6