ADG793A AD [Analog Devices], ADG793A Datasheet - Page 19

• Manufacturer Part Number: ADG793A
• Description: I2C-Compatible, Wide Bandwidth, Triple 3:1 Multiplexer
• Manufacturer: AD [Analog Devices]

LDSW BIT
The LDSW bit allows the user to control the way the device
executes the commands loaded during the write operations.
The ADG793A/ADG793G execute all the commands loaded
between two successive write operations that have set the
LDSW bit high.
Setting the LDSW high for every write cycle ensures that the
device executes the command right after the LDSW bit was
loaded into the device. This setting can be used when the
desired configuration can be achieved by sending a single
command or when the switches and/or GPO pin are not
required to be updated at the same time. When the desired
configuration requires multiple commands with simultaneous
updates, the LDSW bit should be set low while loading the
commands, except the last one when the LDSW bit should be
set high. Once the last command with LDSW = high is loaded,
the device executes all commands received since the last update
simultaneously.
POWER ON/SOFTWARE RESET
The ADG793A/ADG793G have a software reset function
implemented by the RESETB bit from the second data byte
loaded into the device during a write operation. For normal
operation of the multiplexers and GPO pins, this bit should be
set high. When RESETB = low or after power-up, the switches
from all multiplexers are turned off (open) and the GPO pins
are set low.
Bit Map for the ADG793A
RB15
S1A-D1
Bit Map for the ADG793G
RB15
S1A-D1
Read Operation
SDA
SCL
CONDITION
BY MASTER
START
RB14
RB14
S1B-D1
S1B-D1
ADDRESS BYTE
RB13
S1C-D1
RB13
S1C-D1
A2
RB12
RB12
A1
-
-
A0
ACKNOWLEDGE
RB11
S2A-D2
RB11
S2A-D2
R/W
BY SWITCH
RB15
RB10
S2B-D2
RB10
S2B-D2
Figure 32. ADG793A/ADG793G Read Operation
RB14
RB13 RB12 RB11 RB10 RB9 RB8
RB9
S2C-D2
RB9
S2C-D2
Rev. 0 | Page 19 of 24
RB8
RB8
-
-
READ OPERATION
When reading data back from the ADG793A/ADG793G, the
user must begin with an address byte and R/ W bit. The switch
then acknowledges that it is prepared to transmit data by
pulling SDA low. Following this acknowledgement, the
ADG793A/ADG793G transmit two bytes on the next clock
edges. These bytes contain the status of the switches, and each
byte is followed by an acknowledge bit. A logic high bit
represents a switch in the on (close) state while a low represents
a switch in the off (open) state. For the GPO pin (ADG793G
only), the bit represents the logic value of the pin. Figure 32
illustrates the entire read sequence.
The bit maps accompanying Figure 32 show the relationship
between the elements of the ADG793A and ADG793G (that it,
the switches and GPO pins) and the bits that represent their
status after a completed read operation.
RB7
S3A-D3
RB7
S3A-D3
ACKNOWLEDGE
BY SWITCH
RB6
S3B-D3
RB6
S3B-D3
RB7
RB6
RB5
S3C-D3
RB5
RB5
S3C-D3
RB4
RB4
-
RB3 RB2 RB1 RB0
RB4
ADG793A/ADG793G
-
RB3
GPO1
RB3
-
RB2
GPO2
ACKNOWLEDGE
BY SWITCH
RB2
-
RB1
CONDITION
BY MASTER
RB1
-
-
STOP
RB0
RB0
-
-