ADG793A AD [Analog Devices], ADG793A Datasheet - Page 8

• Manufacturer Part Number: ADG793A
• Description: I2C-Compatible, Wide Bandwidth, Triple 3:1 Multiplexer
• Manufacturer: AD [Analog Devices]

ADG793A/ADG793G
Parameter
t
t
t
t
1
2
TIMING DIAGRAM
Guaranteed by initial characterization. C
A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
11
11A
12
SP
1
Conditions
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Fast mode
High speed mode
C
C
C
C
C
C
SDA
SCL
B
B
B
B
B
B
= 100 pF max
= 400 pF max
= 100 pF max
= 400 pF max
= 100 pF max
= 400 pF max
P
t
7
S
B
refers to capacitive load on the bus line, t
Min
20 + 0.1 C
10
20
20 + 0.1 C
10
20
20 + 0.1 C
10
20
0
0
t
6
t
2
t
4
t
11
B
B
B
Figure 2. Timing Diagram for 2-Wire Serial Interface
Max
1000
300
40
80
1000
300
80
160
300
300
40
80
50
10
t
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3
t
1
t
12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
r
and t
f
measured between 0.3 V
S
Description
t
t
condition and after an acknowledge bit
t
Pulse width of suppressed spike
t
RCL
RCL1
FCL
5
t
10
, fall time of SCL signal
, rise time of SCL signal
, rise time of SCL signal after a repeated start
t
6
DD
and 0.7 V
DD
t
8
.
P
t
9